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1、Die-to-Die Interconnect Defect Modeling&Repair ArchitectureMoiz Khan Anshuman Chandra Jonathan Gaudet Siemens 2026|Siemens Digital Industries Software|Tessent|Moiz Khan|2026-02-19Outline Die-to-Die InterconnectDefectsTests Types of Interconnect&DefectMicro-bumpsTSVHybrid Bonds Cluster Defects Interc

2、onnect Repair&Repair Architectures Summary Siemens 2026|Siemens Digital Industries Software|Tessent|Moiz Khan|2026-02-19Die-to-Die Interconnect 2.5D Package Chiplets side by side connected by interposer Passive Interposer:Only wires connecting chiplets 3D Package Multiple chiplets on top of each oth

3、er Die-to-Die Interconnect Physical connection between chiplets/interposer Increasing Interconnect Density,Power&BW needs 2.5D multi-die package3D multi-die package3 nm5 nm7 nmBridges due to wire proximityD2D InterconnectSource:ISSCC:Roadmap on 3D Interconnect Density-EE Times Asia Siemens 2026|Siem

4、ens Digital Industries Software|Tessent|Moiz Khan|2026-02-19Interconnect Defects Manufacturing defects Impact performance of multi-die package Can damage full package Yield$Hard defects:Opens&Shorts Connection fully open or shorted Weak Defect:Weak Opens&Short Interconnect structure not properly for

5、med or damaged Fault Models Stuck-at,transition and bridging fault models Diagnosis Requires unique signature for each defectFunctional logicFunctional logicHard/Weak open(Resistive Open)Hard/Weak short(Resistive Bridges)Die1Die2Stuck-At-0/1(DC)Siemens 2026|Siemens Digital Industries Software|Tessen

6、t|Moiz Khan|2026-02-19Die1Die2Interconnect TestFunctional logicFunctional logicHard/Weak open(Resistive Open)Hard/Weak short(Resistive Bridges)Die1Die2Stuck-At-0/1(DC)DefectTestStuck-at-0/1A fixed 0/1 on each interconnectHard BridgeCreate opposite value at each interconnect pairResistive Open(High-R

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1. **Die-to-Die互连缺陷与测试**: - 硬缺陷(开路/短路)和弱缺陷(电阻性开路/桥接)影响多芯片封装良率,采用增强真值互补(E2I-TEST)测试模式,16种模式覆盖故障模型。 - 微凸块(直径10-40μm)、TSV(直径1-10μm,高宽比>10:1)和混合键合(WoW/CoW,间距400nm/2μm)是主要互连类型,缺陷包括高度变化、空洞、粒子污染等。 2. **混合键合缺陷与修复**: - 粒子污染导致“线效应”和簇状缺陷(如25×50μm区域影响62.5个凸块),需簇级修复(如左移/交换修复)。 - 故障模型包括电阻变化、延迟和短路,需双周期过渡测试和桥接测试。 3. **修复架构与标准**: - 传统修复(如左移/交换)支持单通道修复,但簇缺陷需冗余设计(如3×3凸块MUX)。 - IEEE 1838提供测试访问,IEEE P3405规范互连测试与修复,采用eFuse配置和DWR(Die-to-Die Repair)IP。
**芯片互连缺陷有哪些?** **混合键合如何修复?** **3D封装测试标准是什么?**
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