20260218_B-101_Bunnell.PDF

1、UALink ChipletsVerification Approaches for Heterogeneous Accelerator InteroperabilityJustin Bunnell,VIP ArchitectRise of Compute-Intensive AIModern AI workloads demand immense computational power,requiring thousands of GPUs to work in coordinated clusters for tasks like training large language model

2、s.Interconnect BottlenecksTraditional interconnects like Ethernet and PCIe lack the high throughput and ultra-low latency needed for direct memory sharing between tightly coupled accelerators.Proprietary AlternativesBefore UALink,the industry depended on proprietary technologies,limiting interoperab

3、ility and vendor options for hyper scalers and system designers.The Need for an Open StandardDriven by major cloud providers and chip makers,the UALink Consortium was formed to create an open,vendor-neutral standard to foster a competitive ecosystem2BackgroundUALink Rack-Scale ArchitectureUALink Ove

4、rview3UPLi Upper Layer(App/Protocol Layer)UPLi Flow ControlUPLi Req/Resp generationUALink StationTransaction LayerTo/From Accelerator(Protocol Layer)PHY Layer(Ethernet or PCIe)DL Flit Packing/Unpacking(PCIe:256B/Eth:640B)DL MessagingUART(Ethernet)Tx Pacing/Rx Rate AdaptationUPLi interfaceData Link L

5、ayer(Ethernet Or PCIe)pipe/serial interfaceTL Flit Packing/Unpacking(64B)TL Flow Control TX/RX Address Compression CacheUPLiorigUPLicmplUPLiorigUPLicmpl1x4 to 4x1 200G Ethernet PHY(RS/PCS/PMA)1x8 to 4x2 128G PCIe PHYPL/DL interfaceUALINK IO ChipletUALink Chiplet Opportunity4Monolithic Approach Chall

6、engesHigh development costs for full UALink integrationLimited flexibility in accelerator design/number of stationsDifficult to scale SERDES countLonger time-to-marketChiplet Solution BenefitsSeparation of Concerns:Accelerator logic separate from UALink I/OCost Optimization:Reusable UALink chiplet a