20260218_A-102_Rayane.PDF

1、Thermal Aware Chiplet and Power Pins FloorplanningManaging Hotspots in Chiplet-Based 3D/2.5D IntegrationUnrestricted|Siemens 2025|Siemens Digital Industries SoftwareIyad RAYANE ()Motivation:Why 3D ICs?Unrestricted|Siemens 2025|Siemens Digital Industries Software Chiplet-based integration enables:Hig

2、her performance Higher functional density Heterogeneous integration Vertical stacking reduces interconnect latency 3D and 2.5D architectures are becoming mainstream-SiP:System in Package-MCM:Multi Chip Modules-Chiplets design-System Level Scaling-2.5D/3D ICThermal Challenges in 3D ICsUnrestricted|Si

3、emens 2025|Siemens Digital Industries Software Increased power density due to vertical stackingPower density is higher for a given footprint than for traditional 2D chips Limited heat removal paths Strong thermal coupling between layers Thermal stability causing issues likeThermal stress chip warpag

4、e under compressive stressesMechanical stability ImpactReliability and performance lossPower delivery issues Problem StatementUnrestricted|Siemens 2025|Siemens Digital Industries Software Traditional floorplanning is not thermal-aware Thermal analysis is usually late-stageManual and expert-driven La

5、ck of system-level optimization GoalEnable early-stage thermal-aware floorplanning without requiring thermal expertise Source:Proposed Methodology OverviewUnrestricted|Siemens 2025|Siemens Digital Industries Software A thermal-aware framework that:Optimizes chiplet macro placementConsiders 3D stack

6、structureCan extend to power pin distributionKey ObjectivesReduce peak temperatureImprove heat distributionRespect all physical constraintsUser stack descriptionChiplet and modules modelingInitial floorplanningThermal awareoptimizationExtension to power pin optimizationUser Interface PhilosophyUnres