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20260218_B-102_Kolbehdari.PDF

上传人: 彩旗 编号:1158827 2026-03-02 13页 839.14KB

1、THz/RF Corridors as a General in-package FabricFor Chiplets,HBM,and High-speed Die-die InterconnectAuthor:Dr.Moh KolbehdariDir.of Packaging Architecture,Socionext America Inc.Corridors as the Next Wave of In-Package Interconnect fabricFrom Chiplet Links to a Common In-Package FabricAI/HPC packages a

2、re evolving into dense in-package backplanessupporting multiple protocols and traffic classes.As die counts and distance grow,long in-package links increasinglyface board-level signal integrity and power challenges.This raises a fundamental architectural question for chipletsystems:Do we continue sc

3、aling electrical links alone,or introduceguided RF/EM corridors as a complementary in-packagefabric layer?2What Breaks First in Chiplet-Based PackagesCommon Physical Pain Points:Chiplets,HBM,PCIe,SerDesLong in-package links(chipletchiplet,logicHBM,retimed PCIe/SerDes)encounter:Loss scales with dista

4、nce at multi-GHz/multi-Tb/s.Crosstalk/EMI and exploding keep-out zones.Rising SerDes equalization and power overhead.Different protocols-the same physical symptoms in the package.3These“pain corridors”are where multiple protocols collide with the same physical limits inside the package.What Breaks F

5、irst in Chiplet-Based PackagesExample:Chiplet+HBM floorplanLong in-package electrical links consume routing area and enforce large shielded keep-outs,independent of protocol.These long,shared electrical paths becomethe dominant physical bottleneckbeforeprotocol limits are reached.4Typical electrical

6、 channel length for chipletchiplet or logicHBMChiplet floorplanning on an interposer illustrating long electrical channels,shielded keep-outs,and routing congestion.Guided EM Corridors as a Common Transport LegGuided THz/RF Corridors:A Shared Physical ChannelInsert RF/EM“corridors”as guided wave pat

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1. **问题背景**:AI/HPC封装中长距离片上系统(chiplet)和HBM电气链路面临损耗、串扰/EMI、屏蔽区过大及SerDes功耗开销等物理瓶颈,成为多协议共用的“痛点走廊”。 2. **解决方案**:引入THz/RF波导走廊作为通用封装传输层,通过短电气 stub→波导走廊→短 stub 的结构,替代长距离电气链路,提升隔离性、布线密度和信号完整性。 3. **实现方式**:基于现有硅中介层/RDL工艺,采用TE₁₀模式(180–220 GHz)的金属围栏(via fences)或SIW结构,无需新协议。 4. **应用场景**:chiplet间长距互连、HBM宽接口布线、PCIe/SerDes近边缘聚合,解决布线拥堵和EMI问题。 5. **挑战**:需标准化测试结构、开发走廊PDK、设计混合信号接口宏,首要考虑风险/成本/标准化平衡。
**芯片互联瓶颈?** **THz走廊优势?** **封装 fabric 如何选?**
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