20260218_B-103_Rodriguez.PDF

1、Tackling Electrical Complexity in UCIeCo-Simulation for RTL and Analog Models Luis E.RodriguezJonathan RamirezSiemens EDABackground:Analog vs Logic SimulationAnalog and Logic validation are typically kept separateAnalog Simulation:circuit level,analog accuracy(SPICE)Logic Simulation:Functional Level

2、 RTL simulationAnalog Mixed Signal:Typically done before Tapeout to validate Analog/Digital interactions.Limited test corners due to simulation time2Background:Missed Test CornersCertain corner cases may be missed,and hard to debug in the labMixed-signal boundary bugs:jitter,duty-cycle distortion,am

3、plitude droop can shift sampling pointsCDR/equalization adaptation:dependent on training patterns and channel characteristicsISI/Crosstalk:noise,crosstalk can be data dependent Reset/bring-up race condition:Analog blocks need settle/lock time(PLL,CDR),logic sims typically assume near instantaneous s

4、ettle/lock time3Background:UCIe Channel Performance MetricsIndustry Standard for die-to-die communicationCompliance MetricsVTF LossVTF X-TalkEye Mask Requirements Limitation:Minimal equalization requiredVTF LOSSData Rate(GT/s)4,812,1624,32VTF Loss(dB)L(0)-4.5 L(fN)-7.5L(0)-4.5L(fN)-6.5L(0)-4.5L(fN)-

5、7.5VTF X-TalkData Rate(GT/s)4,812,1624,32VTF X-talk(dB)XT(fN)3*L(fN)-11.5 and XT(fN)-25XT(fN)3*L(fN)-11.5 and XT(fN)-25XT(fN)2.5*L(fN)-10 and XT(fN)-26Eye MaskData Rate(GT/s)Eye Height(mV)Eye Width(UI)4,8,12,1640.7524,3240.65Background:Interoperability and ComplianceInteroperability testing pre-tape

6、out is crucial to ensure multi-vendor,open chiplet marketplaceUCIe Interoperability/Compliance program:several years outNo Golden Model:no single trusted Logic/Analog referenceCompliance Coverage gaps:misses multi-vendor corner casesAnalog-Digital Coupling:Interoperability depends on complex PHY tra