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20260219_H-201_Hung Fung.PDF

上传人: 彩旗 编号:1158873 2026-03-02 17页 1.96MB

1、Demonstrating Optical Data Paths with ChipletsSue Hung FungPrincipal Product Marketing Manager Alphawave Semi,a Qualcomm companyChen SunCo-Founder and VP of Silicon EngineeringAyar LabsOutlineOverview of Alphawave Semi AlphaCHIP1600-IOFunctional DV Testbench and StudyCo-verification test benchUCIe C

2、ompatibility TestingExamples of Tests:LTSM and RetrainSerDes to Optical MCM Design and SI StudyInsertion LossCrosstalkIndustry First,Multi-Protocol I/O Connectivity ChipletAlphaCHIP1600-I/OReconfigurable Multi-Standard 112G SerDes I/OUCIe Compliant D2D interconnectUCIe PHY/Controller IPEthernet and

3、PCIe/CXL SubsystemsUp to 1.6T of throughput at MR,XLR,and PCIe/CXL reachApplicationOptical Driver ChipletExtra Long Reach Ethernet ChipletCombo PCIe/CXL/Ethernet Chiplet1.6T high-speed I/O ChipletAlphaCHIP1600-IOD2D UCIe PHYEthernet and PCIe Combo PHYD2D UCIe PHYMISCPVTDFTCLOCKAlphawave Semi AlphaCH

4、IP1600-IOIndustry First Multi-Protocol 1.6Tbps IO Chiplet Tile Industry First Demonstrator Applications AI and ML IO Disaggregation IO Protocol Translations and Expander UCIe Based Extension Chiplet PCIe Gen6 CXL 3.1 Ethernet 800G SerDes 112G UCIe-Standard PackageEthernet/PCIe/CXL EvalBoardPCIe/CXL

5、EvalBoardPath to Optical Chiplet EnablementD2D for Optical CPOUCIe or similar D2D interface on 2.5D for CPO Alphawave enables an IO Chipletwith:Pre-Silicon Interop Platform Post-Silicon Interop Test VehicleElectrical to Optical -NPOReuse 1.6T chiplet for NPO connections800G Ethernet to UCIeReuse Opt

6、ical Chiplet and IO Chiplet for NPO interceptCurrently working with partners to enable PrototypingC2C Serdes for Copper/Optical We can complement IO chiplets w/co-packaged copper for 112G,224G,448GCopper adds 0 pJ/bit Reuse C2C SerDes for driving new Optical technologyRobust,scalable heterogeneous i

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1. **AlphaCHIP1600-IO芯片**:行业首款多协议1.6Tbps I/O芯片,支持PCIe Gen6、CXL 3.1、800G以太网及112G SerDes,应用于AI/ML IO解耦、协议转换等。 2. **UCIe互操作性**:与Ayar Labs合作,通过端到端测试台验证UCIe兼容性,支持以太网流量透传及光学链路重训练(LTSM/Retrain测试)。 3. **SerDes到光学MCM设计**:43×43mm封装,含2个AlphaCHIP-1600(7nm TSMC)和1个TeraPHY(45nm GF),8个光学端口(每方向512Gbps)。 4. **信号完整性研究**:插入损耗(IL)满足UCIe规范,但串扰(Crosstalk)超标,实际眼图仍保持开放。 5. **异构集成技术**:通过标准化D2D接口(如UCIe)支持CPO(Chiplet on Package)和NPO(Near-Package Optics)方案,铜连接功耗0 pJ/bit。
**1.6T Chiplet优势?** 突出高性能,吸引关注高速互联技术的工程师。 **UCIe兼容性测试?** 聚焦行业热点,吸引关注芯片互操作性的开发者。 **光学MCM设计挑战?** 强调实际应用难点,吸引关注封装设计的专业人士。
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