20260218_H-103_Shankar.PDF

1、Deepak ShankarFounder,Mirabilis DesignThe Coherence Wall:Rethinking Global Cache Across Chiplets(paper S26096)Overview of Mirabilis Design2EDA Software Company based in Silicon ValleyPartner for risk assessment,performance optimization and validation of specificationHighly experience Management and

2、Engineering teamOver 150 man-years of background in semiconductors,automotive and AutomotiveVisualSim Architect Design the Right productSystem-level IP for Architecture ExplorationShift-Left to Shift-Right-A Total SolutionSystem Optimization,Collaboration,Validation,Early Reference Designs and Asset

3、 ManagementNetworkingRF and AnalogAgenda01What is a Coherency Wall?02System Design Challenges in a Multi-Vendor Chiplet03Conducting Design Experiments to Identify the Wall04Analysis and Results05ConclusionWhat is a Coherency Wall?Is the point at which practical scalability limit of cache coherence a

4、cross chipletsBecomes so expensive(in latency,bandwidth,power,and complexity)That system performance stops scaling efficiently4System Design Challenges5How It ManifestsWhen hitting the coherency wall40%interconnect bandwidth consumed by coherence30%stall cycles from remote cache transfersArchitectur

5、e Mitigation7Multi Chiplet Block DiagramUCIeUCIeVisualSim System Model of the SoCChipletChipletChipletChipletChipletExperimentsTo assess Packet Latencies for Read and Write Commands when MESI Protocol is implemented to maintain Cache Coherency.Three test conditions to showcase Latency VariationAll D

6、omains only Read DataAll Domains only Write DataAll Domains perform Read and WriteThe Traffic Generation parameters are:Traffic Generation Interval:0.5 sAddress Range:0,10000 Each Domain picks a random address from this range and sends Read/Write RequestsSimulation Time is set to 100 sVisualSim Syst