20260218_C-103_Eggleston.PDF

1、Chiplets with eFlash IPSession C-103Dave EgglestonSSTWhy Chiplets(part 1)?2Chiplets are needed to extend Moores LawWhy Chiplets(part 2)?3Chiplets beat Monolithic in Cost&Faster TTMAt smaller geometries,volume makes ROI difficult or impossible;hence key motivations for chiplets include:Silicon Re-use

2、 Architecture innovation Integration of die from multiple parties Heterogeneous die,process-optimized Cost constrained yet shorter TTMSource:International Business Strategies(IBS)When Chiplets?4Source:Yole Intelligence,Feb 2023Chiplets for Consumer and Automotive by 2030Where does eFlash go today?MC

3、Us5Low Power MCUMedium Performance MCUHigh Performance MCUADAS MCUThe Many Markets covered by MCUHigh Performance MCU+AI accelerationeFlash IP enables an extremely broad spectrum of marketsWill MCUs follow the processor trend to Chiplets?6TimeServer CPUs Mobile CPUs MPUs MCUs IOHubCoreCoreCoreCoreIO

4、HubCoresCoresDisaggregation2019:AMD,2022:IntelDigital LogiceFlashIORFAnalogFaster TTM&Better flexibility202x:?RFIOAnalogDigital LogicAIEngineeFlashImage Sensor w/AI Source:Sony=XXnm=0YnmAny high volume consumer Chiplet products?eFlash Chiplets offer TTM and flexibility for dMCU7eFlash Chiplets and L

5、ow Cost Assembly8Whether 2D/2.5D or 3D assembly,mismatched chipletsizes can be costly to assemble.SST is working with an Assembly technology vendor to commercialize low cost assembly of mismatched sized chiplets.eFlash Chiplet Options92.5D RDL Fan Out2.5D RDL Fan OutUse RDL(Redistribution Layer)to f

6、an out the chip.Small form-factor,driven by mobile,5G application.In mass production for years.DECA has 600mmx600mm panel process for production.3D Hybrid BondingChip-to-Chip,both have active devices;Nearly Monolithic Integration;CMOS Image Sensor,Sony HBM;AMD V-CacheSST selected 2.5D RDL&Deca Techn