20260218_B-102_Caka.PDF

1、Using UCIe Channel Compliance Simulation for Understanding Substrate/Interposer Design TradeoffsJohn Caka1,Matt Leslie1,Randy Wolff1,Adrien Auge2Siemens EDA,AlphaWave SemiAGENDAWhy Chiplets,Why now?Challenges of 2.5D/3DIC designUCIe Standard OverviewResearch ApproachKey FindingsFuture Work and Concl

2、usionsQ&AWhy chiplets,why now?Reticle SizeHeterogeneous Intg.ModularizationCostYieldBandwidth(Memory)Cost and yield driving alternativesto monolithic solutionsSOC disaggregation into hard IP or“chiplet”sub-functionsMulti-die implementation to avoid reticle limitationsHigher bandwidth/lower powerMemo

3、ry access and proximity,wider bussesShorter/faster interconnectHeterogeneous integrationMix different process and technology nodesLeverage 2.5D/3D assembly platformsChiplet ChallengesTraditional semiconductor design and signoffFit for purpose and manufacturablePackage design and signoffInterposer an

4、d mechanical supportSystem-level multi-physics design and signoffDie level,die-die,package,in-systemMechanical design and signoffWorks in the system contextStress and reliabilityWorks under all operating conditions including thermal induced packaging stressUniversal Chiplet Interconnect Express(UCIe

5、)Industry Standard for die-to-die communicationCompliance MetricsVTF LossVTF X-TalkEye Mask Requirements Limitation:Minimal equalization requiredVTF LOSSData Rate(GT/s)4,812,1624,32VTF Loss(dB)L(0)-4.5 L(fN)-7.5L(0)-4.5L(fN)-6.5L(0)-4.5L(fN)-7.5VTF X-TalkData Rate(GT/s)4,812,1624,32VTF X-talk(dB)XT(

6、fN)3*L(fN)-11.5 and XT(fN)-25XT(fN)3*L(fN)-11.5 and XT(fN)-25XT(fN)2.5*L(fN)-10 and XT(fN)-26Eye MaskData Rate(GT/s)Eye Height(mV)Eye Width(UI)4,8,12,1640.7524,3240.65Research ApproachDoes UCIe minimal equalization underestimate actual performance?IP Vendor EQ CapabilitesCompare UCIe compliance vs.v