20260219_F-202_Ameziane.PDF

1、Scaling Chiplet Verification with Questa One Multi-Die Distributed SimulationKarim Ameziane-Director Product EngineeringFrom Monolithic SoCs to Multi-Die SystemsThe Next Architecture Shiftand a Verification Breaking PointUnrestricted|Siemens 2026|Siemens Digital Industries SoftwareChip Architecture

2、EvolutionWhy Traditional Simulation Breaks Down for Multi-Die SystemsWhen Simulation No Longer ScalesFull-system multi-die simulations often fail to compile,elaborate,or fit into available memoryMulti-die system simulation size and runtime grow beyond typical compute farmsSimulation memory and runti

3、me grow exponentially with each added die due to:Cross-die interconnect modeling complexityProtocol monitors,scoreboards,and checkers across multiple diesEvent propagation and synchronization overheadEven simple multi-die integration testbenches require weeks of additional effort to build and debug

4、delaying time-to-verificationUnrestricted|Siemens 2026|Siemens Digital Industries SoftwareWhy Traditional Simulation Breaks Down for Multi-Die SystemsWhen Simulation No Longer ScalesDistributed simulation for multi-chiplet designs can take days or weeks per run,slowing debug and coverage closureCrit

5、ical interoperability bugs only surface:Under real system traffic patternsUnder true latency&bandwidth pressureAfter billions of cycles with corner-case timingMany teams fall back to:Verifying dies in isolation with simplified BFMsDiscovering failures late in integration or silicon bring-upUnrestric

6、ted|Siemens 2026|Siemens Digital Industries SoftwareUnrestricted|Siemens 2026|Siemens Digital Industries SoftwareMulti-die systems demand a fundamental shift in simulation,faster engines alone are not enough.As systems become distributed,simulation must evolve from faster execution to scalable,parti