20260219_A-203_Wedge.PDF

1、Enabling Advanced Transceiver Verification for Chiplet ArchitecturesScott Wedge,Jessi Lipoth,and Lih-Jen Hou Siemens EDAFebruary 19th,2026The Chiplet ChallengeTest costs must be reduced to make chiplet-based design worthwhile.Test failures are occurring with critical components such as transceivers.

2、Feedback to EDA:“Your system-level tools are good.Your chip-level tools are good.Our failures occur with advanced packaging integration.”“Can you help us shift-left in our verification flow to detect,analyze and fix potential issues much earlier in design?”“The need is particularly acute for chiplet

3、 PHY-layer electrical interfaces as we push for greater bandwidth density.”2A-203:Enabling Advanced Transceiver VerificationThe Chiplet Die-to-Die PHY SI ChallengePHY-layer signal integrity(SI)analysis involves different design tools with different models and algorithms.System-level tools have their

4、 levels of model abstraction and standardsE.g.IBIS,IBIS-AMI Chip-level tools have their levels of model abstraction and standards.E.g.SPICE,Verilog-AMSInterconnect,PEX,EM tools have their standardsE.g.DSPF,Touchstone(S-parameters)Multi-die designs may involve mixed process technologies.How can these

5、 diverse modeling paradigms be combined to achieve a shift-leftfor PHY transceiver verification?3A-203:Enabling Advanced Transceiver VerificationHyperLynx Signal Integrity(SI)Chip/package/board SI analyses to predict signal quality and eye closure due to impedance mismatches,inter-symbol interferenc

6、e(ISI),drive impedance,slew rate,termination,signal spacing,crosstalk,and topology effects.4Import Design DataAssign SI/PI ModelsVia Parameter SetupCoupling SettingsSelect Nets to AnalyzeRun AnalysisAnalyze ResultsAutomatic Extraction of TopologySystem LevelA-203:Enabling Advanced Transceiver Verifi