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20260218_H-103_Nowroozi.PDF

上传人: 彩旗 编号:1158861 2026-03-02 27页 5.37MB

1、1H-103 Chiplet Summit 2026 LIGHTMATTERComposable Interconnect for 400 Gb/s/Lane AI Systems H-103 DesignBijan Nowroozi Head of Ecosystem Development2 2Master Slide TemplateH-103 Chiplet Summit 2026 LIGHTMATTERTHE NETWORK IS BECOMING THE COMPUTER3H-103 Chiplet Summit 2026 LIGHTMATTERThe Trend:Extendin

2、g the Die with IODIEDIEDIEDIEDIEDIEDIEMCM Organic SubstrateLogic+IO w D2DReticle LimitedMonolithic Die2.5D InterposerAbstracted+Disaggregated3D InterposerAbstracted+Disaggregated+Stacked(RDL etc)TransistorDIE ScalingIO Scaling3D IO ScalingDIEDIE4H-103 Chiplet Summit 2026 LIGHTMATTERExtending the Tre

3、nd:Networking Needs More IO224G448G448G224G224G224G800G Link=16 Wires.1 TX channel:2 wires 0101011 RX channel:2 wires 010101 This 102T switch ASIC requires at least 2040 224G traces or wires.112G112G112G112G112G112G112G112GOptical Interconnect Forum(OIF)Common Electrical I/O(CEI)Roadmap 5H-103 Chipl

4、et Summit 2026 LIGHTMATTERTRAYRACKCLUSTERCHIPLETDIEMore Than Moore:The Network Did Become The ComputerScaleOutUpAcrossAt every level,from transistors to clusters,performance is governed by network efficiency.INTER-CONNECT6 6Master Slide TemplateH-103 Chiplet Summit 2026 LIGHTMATTERWhats Standing in

5、the Way?7H-103 Chiplet Summit 2026 LIGHTMATTERThe Interconnect Bottleneck8H-103 Chiplet Summit 2026 LIGHTMATTERStopping Just Short of the GoalWe thought LEGOs.We have a Jigsaw Puzzle.We are paying an Integration Tax that stymies innovation.SerDesPCIeUCiE ABoWLogicUCiE SIEDM 2024 Short Course on AI S

6、ystems and the Next Leap Forward.Victor Moroz,“3DIC STCO for AI Systems”https:/ Chiplet Summit 2026 LIGHTMATTERTodays Scale-up Pod is limited by how many GPUs that can fit within a meter of the connector.Adding retimers to stretch a copper link is expensive(a dead end)in terms of space,spend,latency

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1. **网络即计算机**:AI系统性能受网络效率制约,从晶体管到集群均需高效互连。 2. **互连瓶颈**:传统铜线在448G速率下发热严重(如PCB traces成"烤面包丝"),且1米内密度受限,扩展需昂贵中继器。 3. **光子互连优势**:硅光子技术(如Lightmatter的Passage系列)实现: - 可靠性提升5倍(CPO MTBF 260万小时 vs 可插拔模块55万小时); - 密度达2.0 Tbps/mm(铜线仅0.5 Tbps/mm); - 单光纤支持双向16通道DWDM,传输距离超1公里。 4. **开放芯片let架构**:通过分层设计(电源/控制层、光互连层、逻辑层)抽象化逻辑与互连,降低400G/lane设计门槛,推动开放生态。
**光子互联瓶颈?** **400G/lane如何实现?** **开放芯片let经济?**
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