20260218_B-102_Batada.PDF

1、Enabling Next-Gen Chiplets:UCIe Routing and SI on 8-Metal Silicon InterposerAlphawave SemiChiplet Summit 2026Mohammed Amaan ArabNirmal KshetrapalanAlphawave Semi A Leader in Chiplet Connectivity2Enabling the Industrys First 64 Gbps UCIe IPThe AresCORE PHY IP is a market leading extremely low-power,l

2、ow-latency Universal Chiplet Interconnect Express(UCIeTM)interface IP designed by Alphawave SemiAresCORE can be configured to support advanced packaging such as Chip-on-Wafer-on-Substrate(CoWoS)and Integrated-Fan-Out(InFO)for maximum density,and standard packages such as Organic Substrates for the m

3、ost cost-effective solution covering all market segmentsStrong in-house interposer design expertise,delivering high-density,SI-clean routing architectures that seamlessly enable next-generation chiplet integration for UCIe and HBM with performance,scalability,and manufacturability in mindIndustrys F

4、irst 3nm UCIe IP with CoWoS PackagingOutlineIntroduction&MotivationTechnology&Protocol Interposer Design PlanningUCIe-A routing methodologySignal Integrity for UCIe-AKey Takeaways&Future Scope3The Drive for Multi-Die PackagingYield/Reticle Limit ChallengePerformance and BandwidthHeterogeneous Integr

5、ationChiplets help to extend Moores law by enabling a higher level of integration at the package level 42.5D Advanced Packaging/InterposerAdd-on component between laminated substrate and top dies which provides low loss interconnects and supports fine-pitch bumps5Types of 2.5D InterposersChiplet int

6、egration broadly relies on variant of 3 primary Interposer technologies 6Si InterposerRDL InterposerLSI InterposerSource:Si Interposer with 8 Metals Stack-upPros:Higher number of dedicated layers for signal,power,and shieldingImproved return-path control and impedance consistencyRouting flexibility