20260219_E-202_Peterson.PDF

1、Enabling Flexible Heterogeneous Integration with an eFPGA Chiplet on Intel 18ATrey Peterson QuickLogicIssy Kipnis,Tao Zhou Intel FoundryApplications are constrained by 3 competing requirements2eFPGA Chipletsprovide modular and reconfigurable acceleration01.Performance03.Adaptability02.LongevityUpgra

2、de vs.QualificationTraditional Architectures Force TradeoffsChiplets Localize Change3 Heterogeneous integration:Mix nodes/IP(logic,I/O,memory,.etc)Modular:Upgrade chiplets while preserving qualified baseline Standard interface(UCIe):interoperable die-to-die link that enables reuseMonolithicChiplet-b

3、ased(2.5D/3D)Change-Full respin+requalificationUpgrade one chiplet,preserve qualified baselineIntel 18A Enables High Performance4 RibbonFET for performance and power PowerVia improves IR drop and routing Onshore trusted manufacturingeFPGA Chiplet Overview5GPIO Bank GPIO Bank UCle LinkInterface Logic

4、UCIe AdapterUCIe PHYeFPGA CoreI/OCLBBRAMDSPeFPGA Chiplet Overview6GPIO Bank GPIO Bank UCle LinkInterface logicUCle AdapterUCle PHYeFPGA CoreI/OBRAMDSPCLBConfigurable Logic BlocksCombinatorial and sequential computationeFPGA Chiplet Overview7GPIO Bank GPIO Bank UCle LinkInterface logicUCle AdapterUCl

5、e PHYeFPGA CoreI/OCLBBRAMDSPDigital Signal ProcessingMath heavy operations and timing controlledeFPGA Chiplet Overview8GPIO Bank GPIO Bank UCle LinkInterface logicUCle AdapterUCle PHYeFPGA CoreI/OCLBDSPBlock RAMLocal storage for buffering+coefficientsBRAMeFPGA Chiplet Overview9GPIO Bank GPIO Bank UC

6、le LinkInterface logicUCle AdapterUCle PHYeFPGA CoreCLBBRAMDSPI/OI/O TilesGPIO bank+UCIe interfaceeFPGA Chiplet Overview10GPIO Bank GPIO Bank eFPGA CoreI/OCLBBRAMDSPUCle LinkInterface LogicUCIe AdapterUCIe PHYUCIeInteroperable chiplet boundaryDevelopment Environment11FPGA userQuickLogicFree&OpenSour