20260218_K-4_Das Sharma.PDF

1、UCIe Consortium 2026|Chiplet Summit 2026On-Package Chiplet Innovations with Universal Chiplet Interconnect ExpressTM(UCIeTM)Dr.Debendra Das SharmaChair of UCIe ConsortiumIntel Senior Fellow and Chief Architect I/O Technologies and Standards,DCAI Group,Intel CorporationDisclaimerThe information in th

2、is presentation may refer to a specification still in the development process.This presentation may reflect the current thinking of various UCIe workgroups,but all material is subject to change as specifications are developed.UCIe Consortium 2026|Chiplet Summit 2026AgendaMotivation for Chiplets and

3、UCIeIntroducing UCIeOverview of UCIe:3 Generations of InnovationsKey Metrics of UCIeFuture Directions and Conclusions UCIe Consortium 2026|Chiplet Summit 2026Motivation for Chiplets and UCIe Overcome reticle limits SoC at package level Reduces time-to-solution(e.g.,enables die reuse)Lowers portfolio

4、 cost(product&project)Optimal process Smaller dies=better yieldReduces IP porting costsLowers product SKU cost Bespoke solution Mix-and-match with a standard interface Scales innovation(Mfg.process locked IPs)SiP is the new SoC!SiP is the new platform for innovation with UCIe open standard!Universal

5、 Chiplet Interconnect Express (UCIe)High-bandwidth,Low-latency,Power-efficient,Cost-effective Interconnects forAI,HPC,Cloud,Edge,Enterprise,5G,Automotive,HandheldsUCIe Guiding Principles Open chiplet ecosystem Backward-compatible evolution to ensure investment protection Optimized power,performance,

6、and cost metrics applicable across the entire compute continuum Continuously innovate to meet the needs of the evolving ecosystemLeveraging decades of experience driving successful industry standards at the board level:PCIe,CXL,USB,etc.An Open Standard for Chiplet DevelopmentUCIe Consortium 2026|Chi