20260218_PLEN_Handy.PDF

1、The Chiplet Market Today and Where Its HeadedJim HandyObjective AnalysisWhere Are Chiplets Used Today?That depends on what you call a chiplet!MCMMCMMCPMCPStackedStackedDiceDiceBigBigChipsChipsMixedMixedProcessesProcessesHybridHybridBondingBondingHBMHBM(TSVs)(TSVs)HybridHybridBondingBondingPhoto Cred

2、its:Top,left to right:Intech,Toshiba,Kioxia,AMD/Xilinx,AMDBottom,left to right:Micron/IBM,YMTC,Samsung“Chiplet”:Objective Analysis DefinitionMultiple chips within the same packagethat communicate with each other using signals optimized for in-package commsWhere Are Chiplets Used Today?That depends o

3、n what you call a chiplet!MCMMCMMCPMCPStackedStackedDiceDiceBigBigChipsChipsMixedMixedProcessesProcessesHybridHybridBondingBondingHBMHBM(TSVs)(TSVs)HybridHybridBondingBondingPhoto Credits:Top,left to right:Intech,Toshiba,Kioxia,AMD/Xilinx,AMDBottom,left to right:Micron/IBM,YMTC,SamsungReasons to Use

4、 ChipletsReticle limitLarger chips get lower yieldsMask costsUse expensive process only where advantageousMore SKUsFaster TTM/lower NREDifferent wafer technologies,like memory vs.logic,or opticalSome technologies dont shrink with process(SRAM)Power savingsReticle LimitYield vs.Die Area0%10%20%30%40%

5、50%60%70%80%90%100%0mm40mm80mm120mm 160mm 200mm 240mm 280mm 320mm 360mmYieldDie AreaChiplet vs.Monolithic YieldsMonolithic2 Chiplets3 Chiplets4 ChipletsSource:Objective AnalysisBose-Einstein ModelDefect Density:30/300mm wafer20 Critical LayersLarge Monolithic vs.Small 4-Chiplet ExampleDesignChips Ar

6、ea/DieTotal AreaRelativeCostMonolithic1777mm777mm100%Chiplets4213mm852mm59%Decoupling ProcessesSource:AMDLimit Use of Expensive ProcessesMore SKUs/Time to MarketZen 5Zen 5cFaster Time-to-Market/Lower NREFrom:Extending Verification&Validation to Multi-Die DesignsLevent Caglar(Synopsys),Chiplet Summit