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1、Chiplets for AI Data Centers:Challenges,Shift Left Strategies,3D,Co-Packaged OpticsRobert Kruger,Director of Product ManagementFebruary 2026Legal DisclosureCONFIDENTIAL INFORMATIONThe information contained in this presentation is the confidential and proprietary information of Synopsys.You are not p

2、ermitted to disseminate or use any of the information provided to you in this presentation outside of Synopsys without prior written authorization.IMPORTANT NOTICEThis presentation may include information related to Synopsys future product or business plans.Such plans are as of the date of this pres

3、entation and subject to change.Synopsys is not obligated to update this presentation or develop the products with the features and/or functionality discussed in this presentation.Additionally,Synopsys products and services may only be offered and purchased pursuant to an authorized quote and purchas

4、e order or a mutually agreed upon written contract.FORWARD LOOKING STATEMENTSThis presentation may include certain statements including,but not limited to,Synopsys financial targets,expectations and objectives;business and market outlook,business opportunities,strategies and technological trends;and

5、 more.These statements are made only as of the date hereof and subject to change.Actual results or events could differ materially from those anticipated in such statements due to a number of factors.Synopsys undertakes no duty to,and does not intend to,update any statement in this presentation,wheth

6、er as a result of new information,future events or otherwise,unless required by law.Legal DisclosureCONFIDENTIAL INFORMATIONThe information contained in this presentation is the confidential and proprietary information of Synopsys.You are not permitted to disseminate or use any of the information pr

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1. **Chiplet趋势**:到2030年,≤7nm设计项目中50%以上将采用Chiplet架构,以应对AI数据中心算力需求(IBS 2023数据)。 2. **技术挑战**:需解决系统分区、Die-to-Die互联(如UCIe、PCIe 7.0)、散热、可靠性及安全问题,支持2.5D/3D集成。 3. **解决方案**:Synopsys提供IP子系统(如PCIe、HBM、UCIe)、3D IP(支持F2B/F2F拓扑)及Co-Packaged Optics,降低互连功耗(如UCIe 3D PHY)。 4. **性能提升**:3D集成通过混合键合提升带宽密度(达1M/mm²),互连功耗低至0.05pJ/bit(F2F)。 5. **市场驱动**:AI加速器、网络交换及边缘计算推动Chiplet adoption,需参考设计、封装指南及标准(如UCIe)。
**Chiplet趋势?** **3D集成挑战?** **光学封装优势?**
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