20250121_PreConC_Pisano.PDF

1、Known Good Die Enables Known Good Die Enables Advanced Packaging&Advanced Packaging&ChipletChipletManufacturingManufacturingPat Pisano,Sr.Director Pat Pisano,Sr.Director TD Foundry,Intel FoundryTD Foundry,Intel FoundryTD FoundryAgendaAgendaAdvanced Packaging TrendKnown Good Die in chipleteraDie Sort

2、 capability at Intel FoundrySummary2TD Foundry3ADVANCED PACKAGING ERATimeFlip Chip CeramicFlip Chip Organic&Multi Chip PkgEMIB 2.5DFoveros 3DEMIB3.5DFoveros Direct 3DPackage main function:provide power and signaling from motherboard to dieAdded package value:high density interconnects that enable la

3、rger die complexes from multiple process nodesIntel Foundry Package Technology Intel Foundry Package Technology Expansive EcosystemExpansive EcosystemTD Foundry4ChipletChipletAdvantages&ChallengesAdvantages&ChallengesMoving fromSystem on ChipSystem on ChipToSystem on PackageSystem on PackageModular

4、Manufacturing at work:Intel Data Center GPU Max-Product Validation post chipletre-integration,Are manufacturing screens needed-Chipletdiscrete reliability-Integrated reliability-MFG flow:Chip to wfrVS.wfrto wfr-3D stacking?-Package architecture&memory integration-Si Bump to bump connection;-IO Si bu

5、mp scaling-Testing for interconnect quality/reliabilityAdvantagesAdvantagesManufacturing ChallengesManufacturing ChallengesTD FoundryScaling trends due to CHIPLETsScaling trends due to CHIPLETs5Trending 1Trillion transistors per package1.0E+061.0E+081.0E+101.0E+121.0E+142000200520102015202020252030T

6、ranistor CountYearTransistor Trend Over YearsSource:Wikipedia:Transistor Count2D/MCP2.5D2.5D/3DHybrid BondingTrillionsTrillions1T 100T 1M 1B Disaggregation is a potential accelerant to system level transistor count Criticality to Test Capability/Cost and Yield100um020um60um0100200Bump Pitch#Chiplets