20250122_B-101_Chandra.PDF

1、Chiplet Interconnect Test and Repair Using Test StandardsAnshuman Chandra and Martin KeimSiemens EDAExpectations from the Interconnect StandardDFT ArchitectureTest patternsInterconnect repairOn-chipOff-chipDiagnosis&debugPlug&Play across different interfacesCompatible across different EDA toolsAgnos

2、tic of the functional protocolCompatible with other IEEE test standardsTraditional Test Flow3DFTTestDiagnosis&DebugMission mode (In-field)Test Flow in 3D IC Era4DFTTestDiagnosis&DebugD2D Repair(ATE)Mission mode (In-field)Repair (In System)Chiplet Interconnect TypesRepair resource type:Active vs Pass

3、iveOnly Signals between chiplets considered for repairData busControl signalsTiming sensitive signalsClocksSingle or Mulitple domainSerial high speed busSERDES based communicationUse redundant signals to repair defective interconnectsDo we want to include power distribution nets?5Universal Chiplet I

4、nterconnect Express(UCIe):MainbandUnidirectional signalingPackageStandard package:100-130 mAdvanced package:15-55 mBasic module data widthStandard package(UCIe-S):x16(16 TX,16 RX)Advanced package(UCIe-A):x64(64TX,64 RX)RepairStandard package:NoneAdvanced package:DATA:2 bits per 32 bitsClock and Trac

5、k share a repair resourceValid lane repair supportedDifferential forward clock6Universal Chiplet Interconnect Express(UCIe):SidebandSideband is used for:TrainingDebugManagementSerial Data and clock pairSingle Data Rate(SDR)signal at 800 MHz clock frequencySideband repairStandard package:NoneAdvanced

6、 package:Both clock and data redundancy7Test Architecture:Non-configurable vs ConfigurableHBM(Non-configurable)WayConfigurable WayChiplet2Chiplet1R1R1BISTBISTBIRABIRAeFuseeFuseTAP/1500/1838TAP/1500/1838Chiplet1(SOC)PADS/PHYWDR1500 IP ControllerChiplet2(HBM)PADS/PHYWDR1500 Test Access WSIWSOInterconn