Session4_Analog Techniques & Amplifiers.pdf

1、ISSCC 2026SESSION 4Analog Techniques&Amplifiers1 of 39 2026 IEEEInternational Solid-State Circuits Conference4.1:A 0.64mA,-108.2dB THD+N Class-D Amplifier with Neural-Assisted Pre-Reconfiguration for Smart Power OptimizationA 0.64mA,-108.2dB THD+N Class-D Amplifier with Neural-Assisted Pre-Reconfigu

2、ration for Smart Power OptimizationKaiwen Zhou,Yuxiang Tang,Zhongqiu Shen,Xuecheng Yang,Tianxiang Qu,Yiming Wang,Shen Ye,Zhiliang Hong,Jiawei XuFudan University,Shanghai,China2 of 39Low Quiescent Current(90%)Challenge:Battery Life3 of 39Challenge:Quiescent Current and Efficiency 2026 IEEEInternation

3、al Solid-State Circuits Conference4.1:A 0.64mA,-108.2dB THD+N Class-D Amplifier with Neural-Assisted Pre-Reconfiguration for Smart Power Optimization Power stage Consumption:Large quiescent current consumptionEfficiency degradation at low output level4 of 39 2026 IEEEInternational Solid-State Circui

4、ts Conference4.1:A 0.64mA,-108.2dB THD+N Class-D Amplifier with Neural-Assisted Pre-Reconfiguration for Smart Power OptimizationSwitching loss in power stage:Dominated by charging/discharging of power during idle operationChallenge:Switching Loss5 of 39 2026 IEEEInternational Solid-State Circuits Co

5、nference4.1:A 0.64mA,-108.2dB THD+N Class-D Amplifier with Neural-Assisted Pre-Reconfiguration for Smart Power Optimization Reducing fSW:Limited by loop-stability constraintTypical fUG 100kHz,fSW 350kHzChallenge:Switching Loss vs.Stability6 of 39 2026 IEEEInternational Solid-State Circuits Conferenc

6、e4.1:A 0.64mA,-108.2dB THD+N Class-D Amplifier with Neural-Assisted Pre-Reconfiguration for Smart Power Optimization Reducing fSW:higher THD due to PWM-residual aliasingChallenge:Switching Loss vs.THD7 of 39 2026 IEEEInternational Solid-State Circuits Conference4.1:A 0.64mA,-108.2dB THD+N Class-D Am