Session12_Frequency Synthesizers and VCOs.pdf

1、ISSCC 2026SESSION 12Frequency Synthesizersand VCOs12.1:A 74fs-Jitter,-59dBc-Spur Fractional-N DPLL Using a Supply-Resilient Time-Amplifying Dual-Ramp DTC 2026 IEEE International Solid-State Circuits Conference1 of 70A 74fs-Jitter,-59dBc-Spur Fractional-N DPLL Using a Supply-Resilient Time-Amplifying

2、 Dual-Ramp DTCRishabh Gurbaxani1,Cicero S.Vaucher1,2,Masoud Babaie11Delft University of Technology,The Netherlands2NXP Semiconductors,Eindhoven,The Netherlands12.1:A 74fs-Jitter,-59dBc-Spur Fractional-N DPLL Using a Supply-Resilient Time-Amplifying Dual-Ramp DTC 2026 IEEE International Solid-State C

3、ircuits Conference2 of 70Outline Motivation Evolution of the Time-Amplifying Dual-Ramp(TADR)DTC DTC nonlinearity and calibration Measurement results Conclusion12.1:A 74fs-Jitter,-59dBc-Spur Fractional-N DPLL Using a Supply-Resilient Time-Amplifying Dual-Ramp DTC 2026 IEEE International Solid-State C

4、ircuits Conference3 of 70Generalized Fractional-N DPLLDCOMMDIVLoop filterPhase detection tasks:Extract tePredict TQby computing Qn TDCO Subtract TQfrom teto obtain tnM-Qn+REFDCOTDCOREFtnPhase Detectorte=TQ+tntn=teQn TDCODIV+Qnt01DIVFCWFRACFCWINT12.1:A 74fs-Jitter,-59dBc-Spur Fractional-N DPLL Using

5、a Supply-Resilient Time-Amplifying Dual-Ramp DTC 2026 IEEE International Solid-State Circuits Conference4 of 70Phase detection using DTC+TDC DCOMMDIVLoop filterM-Qn+REFePhase DetectorDIV+DTCTDCREFdlyTDCO/K?DTC(KDTC)Digital-to-Time-Converter(DTC)removes TQDTC gain calibrated using LMS loopTime-to-Dig

6、ital-Converter(TDC)measures noiseFCWFRACFCWINTg.eDTC gain calibration12.1:A 74fs-Jitter,-59dBc-Spur Fractional-N DPLL Using a Supply-Resilient Time-Amplifying Dual-Ramp DTC 2026 IEEE International Solid-State Circuits Conference5 of 70Challenge 1:Supply Sensitivity of DTCDCOMMDIVLoop filterM-Qn+REFe