1、ISSCC 2026SESSION 27Frequency Generators,Multipliers,and Modulators27.1:A 20-GHz Frequency Synthesizer with Spur-Shaping Modulator Achieving 46.2-fs Jitter and 76.5 dBc Worst-Case Fractional Spur 2026 IEEE International Solid-State Circuits Conference1 of 39A 20-GHz Frequency Synthesizer with Spur-S
2、haping Modulator Achieving 46.2-fs Jitter and 76.5 dBc Worst-Case Fractional SpurZonglin Ye,Yuxuan Sun,Longxiang Hou,Yuhan Ding,Yixuan Wen,Hongyang Zhang,Xinlin Geng,Qian Xie,Shiheng Yang,Zheng WangUniversity of Electronic Science and Technology of China27.1:A 20-GHz Frequency Synthesizer with Spur-
3、Shaping Modulator Achieving 46.2-fs Jitter and 76.5 dBc Worst-Case Fractional Spur 2026 IEEE International Solid-State Circuits Conference2 of 39Outline Motivation Spur-Shaping Modulator Circuit Design Measurement Results Conclusion27.1:A 20-GHz Frequency Synthesizer with Spur-Shaping Modulator Achi
4、eving 46.2-fs Jitter and 76.5 dBc Worst-Case Fractional Spur 2026 IEEE International Solid-State Circuits Conference3 of 39Review Noise shaping utilized to reduce quantization noise(QN)The interaction between nonlinearity of loop and quantization error generates spursPFD+CPw/NonlinearityMMDNint+ynDe
5、lta-Sigma ModulatorfrefFCWynfvcofdivFromReferenceOscillatorFromVCOV.Mazzaro,TCAS-I211.QN suppression2.Good linearity27.1:A 20-GHz Frequency Synthesizer with Spur-Shaping Modulator Achieving 46.2-fs Jitter and 76.5 dBc Worst-Case Fractional Spur 2026 IEEE International Solid-State Circuits Conference
6、4 of 39Review Classic CPPLL No suppression for quantization noise Large residue range due to high-order DSM Immune to inter-slice mismatchN Slices CPPFDfrefMMDNint+ynDelta-Sigma ModulatorFCWynfvcoIoutM.Kennedy,ISSCC24LargeResidueRange27.1:A 20-GHz Frequency Synthesizer with Spur-Shaping Modulator Ac