在 RISC-V 中实现运行时可配置字节序：挑战与解决方案.pdf

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1、1RISCV Big EndianCOPYRIGHT CODETHINK|LICENSED UNDER CCBY SA 4.0RISCV EU Summit 2025CODETHINK201IntroductionCOPYRIGHT CODETHINK|LICENSED UNDER CCBY SA 4.0Endianness What is Endianness?The order values are composed in memoryBig Endian BE left-to-rightLittle Endian LE right-to-leftAn easy way to rememb

2、er:Big/Little endian stores the Big/Little end of the number in the first memory address.3COPYRIGHT CODETHINK|LICENSED UNDER CCBY SA 4.0Different Endians?Different Users?Big Endian:Little Endian:Often used in older architectures and applicationsMany networking protocols use BE.LE systems have to rev

3、erse byte order(adding overhead)x86 chose little endian as at the time,it made operations such as type casting is easier(as memory layout doesnt change)x86 used it and achieved dominance4COPYRIGHT CODETHINK|LICENSED UNDER CCBY SA 4.0Why are we interested?Current state:Definition of Done:RISCV is LEL

4、atest ISA specification adds runtime configurable endianness Part of ISA volume II,privileged architecture Configuration added(version 1.12,2022Overall:Linux running on Qemu in big endianQemu Add ability to configure CSRs and modify data accessesOpenSBI Boot system in big endian and correctly deal w

5、ith IOLinux Build minimal kernel and userland5COPYRIGHT CODETHINK|LICENSED UNDER CCBY SA 4.0602QEMUCOPYRIGHT CODETHINK|LICENSED UNDER CCBY SA 4.0CPU FlagsGoal is to update the CSRs that controls the endian for each execution level M/S/U M-mode is controlled by bit 37(MBE)of the mstatus CSR MBE is th

6、en read-only cloned into bit 36(SBE)and bit 6(UBE)CSR writes allowed to mstatus bits Writes update new context field:ctx-be_dataFor QEMU sstatus SBE and UBE are read-only clones of mstatus We may add SBE/UBE configuration later#define MSTATUS_MBE 0 x2000000000ULL7COPYRIGHT CODETHINK|LICENSED UNDER C