AArch64 和 RISC-V 的 GCC 代码生成器对比分析.pdf

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1、RISC-Vvs.AArch64Comparative Analysis of GCC CodegenPaul-Antoine ArrasComparative Analysis of GCC Codegen for AArch64 and RISC-V|Paul-Antoine Arras|RISC-V EU Summit 2025OutlineContextExperimental setupResults overviewWeaknesses and deficienciesCompilerISALibraryImplementationFuture work2Comparative A

2、nalysis of GCC Codegen for AArch64 and RISC-V|Paul-Antoine Arras|RISC-V EU Summit 2025ContextCollaboration:BayLibre+Rivos+RISEFact:RISC-V GCC trails AArch64 GCCSPEC benchmarksHow to improve compiler codegen?Large gains can be madeVendor-neutral metric:dynamic instruction count(DIC)Analyse assembly i

3、n hotspots(aka top blocks)3Comparative Analysis of GCC Codegen for AArch64 and RISC-V|Paul-Antoine Arras|RISC-V EU Summit 2025Experimental setupTarget architecturesARM64(aka AArch64)SVE2RISC-V RV64GCV256-bit vectorsSPEC CPU 2017 v1.1.9,ref data setGNU toolchain(8 Aug 24)AArch64:-mabi=lp64-march=armv

4、9-a+sve2-msve-vector-bits=256RISC-V:-mabi=lp64d-march=rv64gcv_zvl256b_zba_zbb_zbs_zicond-mrvv-vector-bits=zvlUser-mode QEMU v9.1.0-rc1 with Rivos pluginAArch64:QEMU_CPU=max,sve256=onRISC-V:QEMU_CPU=rv64,vlen=256,v=true,vext_spec=v1.0,zve32f=true,zve64f=true,zba=true,zbb=true,zbc=true,zbs=true,zicond

5、=true,zfhmin=true456Comparative Analysis of GCC Codegen for AArch64 and RISC-V|Paul-Antoine Arras|RISC-V EU Summit 20257ISA:Missing scaled addressing mode510.parest_rDIC+54%vs.AArch64Top block#056%of the runwhile(val_ptr!=val_end_of_row)s+=*val_ptr+*src*colnum_ptr+;3x dereference-incrementThree oper

6、ands(1)Base address(2)Index(3)Element size:4 bytesEffective address:(1)+(2)(3)AArch64ld1wz30.s,p7/z,x3,x0,lsl#2RISC-Vaddit1,t1,16vle32.vv4,(t1)Comparative Analysis of GCC Codegen for AArch64 and RISC-V|Paul-Antoine Arras|RISC-V EU Summit 2025Compiler:Vector-scalar instructionsvfm