用于后量子密码的基于 RISC-V 的加速器.pdf

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1、A RISC-V BASED ACCELERATOR FOR POST QUANTUM CRYPTOGRAPHYAmbily Suresh,Manuel Freiberger,Andrew Wilson,Diego Gigena-Ivanovich,Willibald Krenn010203040506OVERVIEWRISC-V Research at SALThe ISOLDE ProjectRISC-V Accelerators for the EdgePQC The Classic McEliece AlgorithmHW and SW ImplementationSummary an

2、d Future workWhat do we do?SILICON AUSTRIA LABSSilicon Austria Labs GmbH3Silicon Austria Labs(SAL),established in 2018,is a European R&D center with a focus on the development of efficient and trustworthy technologies in the field of electronic systems.Industry-oriented researchR&D servicesWell-equi

3、pped research infrastructuresCustomized opportunities for co-operationTHE ISOLDE PROJECTSilicon Austria Labs GmbH4HIgh Performance,Safe,Secure,Open-Source Leveraged RISC-V Domain-Specific EcosystemsChips-JU+FFG funding for Austrian partnersMay 2023 to April 2026Around 40 partners from 9 countriesEnh

4、ance European high-performance RISC-V-based Systems-on-a-Chip(SoC)Development of advanced architectures,novel accelerators,and reusable IPsThis research received funding from the Austrian Research Promotion Agency and the Austrian ministry for Climate Action,Environment,Energy,Mobility,Innovation,an

5、d Technology under project FO999899263 and the Chips Joint Undertaking and its members Austria,Czechia,France,Germany,Italy,Romania,Spain,Sweden,and Switzerland under the ISOLDE project(no.101112274)RISC-V TOPICS SALSilicon Austria Labs GmbH5Post Quantum CryptographyEvaluate candidate algorithms for

6、 hardware implementationQuantum-safe encryption for resource constrained,edge environmentsEdge AIMinimize privacy risks through local AI acceleration.Speed up neural network processing for efficient,low-latency AI on edge devicesIntegration with RISC-V platformCustomizable and cost-effective RCHW-SW