利用 RISC-V 跟踪标准实现高效的错误修复和性能分析.pdf

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1、Utilizing RISC-V Trace Standards forEfficient Bugfixing and ProfilingNicolas Delemarre|Lauterbach GmbH|13.05.2025 LDriven by market requirements,embedded systems and chip architectures are becoming more complex:More powerful processors of different architectures like RISC-V in different multicore co

2、nfigurations(SMP,AMP).Different operating systems such as Linux as a rich operating system,RTOS or an AUTOSAR variant in the automotive industry.Heterogeneous multicore architectures increasethe requirements for bug fixing and thus for bothpure debuggers and real-time trace.3Challenges Embedded Deve

3、lopers are Facing TodayLRISC-V External Debug Support“Specification v1.0.0 incorporates everything neededfor simple and complex debugging scenariosGreat solution for simple and fairly complex RISC-V SystemsOpen to adaptions to support most complex and diverse SoCsFlexible DTM designs make heterogene

4、ous debugging easySeveral options to add peripheral IP such as TraceRISC-V Debugging Made EasyLWe can freeze the coreWe might freeze also some peripheralsBut we can not freeze the surrounding 5From Debug to TraceEngine ControlCPUTimerUARTGPIOSTOPSTOPSTOPSTOPHow can we still find bugs?LTrace based de

5、buggingDebug without stopping the CPUFind bugs which appear only in real timeOptimizing with timing measurementsAnalyse the code performance of the applicationAnalyse outside eventsQualificationProve the meeting of real time requirementsProve code coverage6Trace Supplements DebuggingLSpecifications

6、for two RISC-V Trace Standards have been ratified recentlyRISC-V E-Trace StandardRISC-V N-Trace StandardStandards consist of different documents7RISC-V Trace SolutionsLRISC-V trace specifications are also suitable for heterogeneous systemsFlexible ways to access the trace components configuration re