20260219_E-202_Surana.PDF

1、Verification of a Silicon BridgeSatish Surana IntelSr.Principal Engineer in Advanced Packaging Technology and ManufacturingSadha Parasuraman IntelDesign Methodology EngineerMichael Walsh Siemens EDATechnical Director IC Packaging and 3DIC SolutionsAbstractWith silicon interposer technologies reachin

2、g their limits due to reticle size constraints,silicon bridge solutions are emerging as the solution of choice for HPC applications.Silicon bridge solutions offer comparable performance with the advantage of larger size substrates allowing for more compute and memory.A state of the art silicon bridg

3、e based substrate poses a complex verification challenge.Die scaling,bump compensation,and the sheer volume of interconnect between die all contribute to the complex verification required to satisfy DRC and LVS.Intel Foundry and Siemens have worked together to provide a robust 3DIC verification proc

4、ess which addresses the challenges of the verification task.This paper will outline the challenges,describe a solution,and recommend best practices to allow design teams close verification quickly and the confidence the design is correct and tapeout ready.1/30/2026Intel Foundry|Siemens EDA|3DIC Veri

5、fication|Chiplet Summit 2026|MW2Intel EMIB TechnologyAdvanced applications,such as AI,machine learning(ML),and high-performance computing(HPC),require high data throughput and low latency.Embedded Multi-die Interconnect Bridge(EMIB)improves semiconductor designs performance,power efficiency,and flex

6、ibility.EMIB enables you to integrate more components as needed,making it easier to scale up performance and functionality without complete system redesigns.EMIB is the industrys first 2.5D interconnect solution using bridges embedded in the substrate.In high-volume manufacturing since 2017,EMIB fea