20260219_E-202_Krishna.PDF

1、Assuring SoC Power Integrity with Silicon CapacitorsMukund KrishnaSr.Manager,Product MarketingEmpower SemiconductorAgendaImpact of Chiplets on Power IntegritySilicon Capacitors Solve the ChallengePrimer on Silicon CapacitorsCapacitor ParametricsPackaging Options for Silicon CapacitorsApplications2In

2、troduction Trends:oAI/HPC driving exponential density&performanceoDisaggregated IPs Chiplets amplify the#of power domains&connectivity Task:oPI/System engineers tasked with power integrity for all sub-systems:VR(active)+Capacitors(passive)oTypically addressed by network of de-coupling capacitors “fl

3、atten”impedance Challenge:oCommon solution is MLCC:form-factor and characteristics generally suitableoMounting limitations and impedance leads to peaking:High noise/low margin,degraded performance3MLCCs with varying case sizePCBPackage SubstratePWRGNDChipletDie-side Capacitors(stub connections)Chipl

4、etw/die capHigh C+High ESL(100pH)Low C+Med ESL(50-100pH)InterposerThe Challenge for Power Integrity4Standard approach:Network of reducing case-size capacitors on PCBSome embedded MLCCs(2-4 terminal):relatively high ESL Large#of components required to meetimpedance targetStruggle to meet noise(mV p-p

5、)specsNetwork of capacitors required to“Flatten”the PDN all the way to 1 GHz+Equivalent MLCCs required:10 x 10uF Effective Capacitance=80uFEffective ESL=40pHTrace L 800pH18x 100FMLCCPCB725 15x 47FMLCCTrace L 100pH725 Trace L 20pHPackage substrate1m 5FDie200 2m 6.5nHVRM80F150 40pHACTarget Impedance L

6、ow C+MedESL(50pH)PCBPackage SubstratePWRGNDInterposerSilicon Capacitors the Solution Orders of magnitude lower ESL:HigherPerf/Power!oLot fewer components to achieve the PDN goaloLower Noise/eliminate peaking:flat PDN PDN ExampleoOriginal solution:high peaking in 6-20MHz range oEmbedding Silicon Caps