用于人工智能规模化发展的节能型光子互连.pdf

1、Jeff HutchinsRanovus,CTO OfficeOIFs PLL WG Vice Chair of Energy Efficient InterfacesEnergy efficient photonic interconnects for AI scale-upEnergy efficient photonic interconnects for AI scale-up,the requirementsJeff HutchinsRanovus,CTO OfficeOIFs PLL WG Vice Chair of Energy Efficient InterfacesThe O

2、IF has engaged with end-users and companies across the eco-system to define the AI Compute requirementsAlthough our focus is on scale-up interconnects,end users are interested in re-using the scale-up optical transceivers for other links with the AI compute PodIt often seems that the various require

3、ments are confusing and sometimes appear contradictory.The presentation attempts to explain the rationale for the various requirementsEnergy efficient interconnects for AI scale-upLinks in an AI Compute PodThere are broadly 5 types of links used in an AI Compute Pod4 4Scale-out(UEC/InfiniBand/Ethern

4、et/etc.)3 3Scale-up (UALink/UEC/NVLink/SUE,etc.)5 5EthernetMemory I/F(CXL/PCIe)2 2HBM I/F Compute I/O1 1(PCIe/CXL/D2D/UCIe)Pods are aggregated with scale-out linksThere are broadly 5 types of links used in AI ComputeFront-end SwitchesScale-out SwitchScale-out SwitchMemory I/F(CXL/PCIe)Compute I/O2 2

5、5 51 13 34 4HBM I/F Scale-out(UEC/InfiniBand/Ethernet/etc.)Scale-up (UALink/UEC/NVLink/SUE/etc.)Ethernet(PCIe/CXL/D2D/UCIe)AI Compute RequirementsKey requirements from hyperscalers are summarized in the tableWe will focus on the requirements for link types 3&4 What reaches are needed?Scale-up reache

6、s are shorter than scale-out reachesDual rack PodDual rack PodScale-up(low latency within Pod links)Scale-out(low latency between Pods)Scale Out SwitchScale Out SwitchScale Out Switch 100m,typically optics today 20m,typically copper today3 34 4Dual rack PodLatencySenderTimeReceivert=0t=1t=2t=3Very s