8.RISC-V MMU Verification of Virtualization and Hypervisor Operation for CPU and SOC Platforms.pdf

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1、RISC-V MMU Verification of Virtualization and Hypervisor Operation for CPU and SOC platformsRISC-V Summit China 2025Adnan Hamid,CTO,Breker Verification SystemsAgendalWhydoweneedMMUs?lVirtualMemoryandPageTableWalkslRISCVISAMMU&HypervisorSpecificationlRISCVMMU&HypervisorTestPlanlExampleMMUTestCaseslDe

2、bug,CoverageandDeploymentBrekerVerificationSystems,Inc.Allrightsreserved2AgendalWhydoweneedMMUs?lVirtualMemoryandPageTableWalkslRISCVISAMMU&HypervisorSpecificationlRISCVMMU&HypervisorTestPlanlExampleMMUTestCaseslDebug,CoverageandDeploymentBrekerVerificationSystems,Inc.Allrightsreserved.3Motivation f

3、or MMU(1/3)BrekerVerificationSystems,Inc.Allrightsreserved.4Attribution:https:/ for MMU(2/3)BrekerVerificationSystems,Inc.Allrightsreserved5Attribution:https:/ for MMU(3/3)BrekerVerificationSystems,Inc.Allrightsreserved.6Attribution:https:/ Memory MappingBrekerVerificationSystems,Inc.Allrightsreserv

4、ed.8Attribution:https:/ to Physical mapping via Page TablesBrekerVerificationSystems,Inc.Allrightsreserved.9Attribution:https:/ to Physical mapping via Page TablesBrekerVerificationSystems,Inc.Allrightsreserved.10Attribution:https:/ Stage Address Translation Page Table WalksBrekerVerificationSystems

5、,Inc.Allrightsreserved.11Attribution:https:/clownote.github.io/2021/03/06/xv6/Xv6-page-table/BuildupsparsetreeofpagedirectoriesS/UmodeHypervisor and Two-Stage Address Translation BrekerVerificationSystems,Inc.Allrightsreserved.12Attribution:https:/clownote.github.io/2021/03/06/xv6/Xv6-page-table/vsa

6、tphgatpGuestVirtualAddress(GVA)GuestPhysicalAddress(GPA)PhysicalAddress(PA)virtual-VS/VU-modeAgendalWhydoweneedMMUs?lVirtualMemoryandPageTableWalkslRISCVISAMMU&HypervisorSpecificationlRISCVMMU&HypervisorTestPlanlExampleMMUTestCaseslDebug,CoverageandDeploymentBrekerVerificationSystems,Inc.Allrightsre