1、1A D-Band CMOS Transceiver Chipset Supporting 640Gb/s Date Rate with 44 Line-of-Sight MIMOASP-DAC UDC 2025Chenxin Liu1,Zheng Li1,Yudai Yamazaki1,Hans Herdian1,Chun Wang1,Anyi Tian1,Jun Sakamaki1,Han Nie1,Xi Fu1,Sena Kato1,Wenqian Wang1,Hongye Huang1,Shinsuke Hara2,Akifumi Kasamatsu2,Hiroyuki Sakai1,
2、Kazuaki Kunihiro1,Atsushi Shirane1,and Kenichi Okada11Institute of Science Tokyo,Tokyo,Japan E-mail:liucxssc.pe.titech.ac.jp2National Institute of Information and Communications Technology,Tokyo,JapanBackground and Motivation2S.Lee et al.JSSC 2019K.K.Tokgoz et al.ISSCC 2018A.Karakuzulu et al.JSSC 20
3、23 Frequency Band Over 100GHz Data Rate exceeds 100Gb/s Ultra-low latency Massive CapacitySmart CarHigh Data RateVR/AR DeviceMulti-Chips3D DeviceProposed D-Band CMOS TRX Chipset3Heterodyne Architecture Front-End RF TX/RX Chipset.External IF/LO signals.Wideband&High-linearity Signal Chain.Transceiver
4、 Chipset Micrograph and PCB Photo4Wideband&Low-Loss PCB IF/LO/RF Interface.RF port utilizes waveguides to connect horn antenna.SISO Wireless Measurement5MIMO Wireless Measurement6Performance Comparison78Thank You9Reference1 S.Lee et al.,An 80-Gb/s 300-GHz-Band Single-Chip CMOS Transceiver,in IEEE Jo
5、urnal of Solid-State Circuits,vol.54,no.12,pp.3577-3588,Dec.2019.2 K.K.Tokgoz et al.,A 120Gb/s 16QAM CMOS millimeter-wave wireless transceiver,2018 IEEE International Solid-State Circuits Conference-(ISSCC),San Francisco,CA,USA,2018,pp.168-170.3 C.Wang et al.,A Sub-THz Full-Duplex Phased-Array Trans
6、ceiver with Self-Interference Cancellation and LO Feedthrough Suppression,2023 IEEE Symposium on VLSI Technology and Circuits(VLSI Technology and Circuits),Kyoto,Japan,2023,pp.1-2.4 A.Karakuzulu,W.A.Ahmad,D.Kissinger and A.Malignaggi,A Four-Channel Bidirection