SESSION 30 Nonvolatile Memory and DRAM.pdf

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1、ISSCC 2025SESSION 30 Nonvolatile Memory and DRAM30.1 A 28Gb/mm24XX-Layer 1Tb 3b/cell WF-Bonding 3D-NAND Flash with 5.6Gb/s/pin IOs 2025 IEEE International Solid-State Circuits Conference1 of 24A 28Gb/mm2 4XX-Layer 1Tb 3b/cell WF-Bonding 3D-NAND Flash with 5.6Gb/s/pin IOsSang-Soo Park,Jae-Doeg Lyu,My

2、ungjun Kim,Jaeyun Lee,Younsun Song,Chung-Ho Yu,Hirano Makoto,YongseokKwon,Jong-Hoon Park,Ho-Joon Kim,Daein Lee,Donghyun Seo,Byungrok Go,Seoyoon Jeon,Yoonjee Kim,Doo-Hyun Kim,Youngmin Jo,Hyunjun Yoon,Junehong Park,Inmo Kim,Sunghoon Kim,Hokil Lee,Je-Hyeon Yu,Sang-Lok Kim,Hwan-Seok Ku,Jungmin Seo,Jindo

3、 Byun,Seung-Hyeon Yun,Kyoungtae Kang,Seung-Beom Kim,YohanLee,Yongkyu Lee,Kyunghwa Kang,Han-Jun Lee,Younghwan Ryu,Hyundo Kim,Wontae Kim,Hyeongdo Choi,Juho Jeon,Ansoo Park,Raehyun Song,Jae-Hwan Kim,Jung-Soo Kim,Hwa-Seok Lee,Moo-Kyung Lee,Jae-Ick Son,Jiho Cho,Moosung Kim,Jae-Woo Im,Jongmin Park,Hyuckjo

4、on Kwon,Youngdon Choi,Chiweon Yoon,SeungjaeLee,Kiwhan Song,Sung-Hoi HurSamsung Electronics,Hwaseong,Korea30.1 A 28Gb/mm24XX-Layer 1Tb 3b/cell WF-Bonding 3D-NAND Flash with 5.6Gb/s/pin IOs 2025 IEEE International Solid-State Circuits Conference2 of 24Outline IntroductionNAND ChallengesMerits of BV-NA

5、ND Architecture(IO,Bit-density)Key Features Key Design2-Transistor Coded-GSLStack-Dependent Pass-Voltage ControlExternal Power Assisted Core DrivingProposed SCA protocol with/ODTLow power High speed IO scheme for 5.6-Gb/s/pin(PI-LTT,DFE,RDCA)Conclusion30.1 A 28Gb/mm24XX-Layer 1Tb 3b/cell WF-Bonding

6、3D-NAND Flash with 5.6Gb/s/pin IOs 2025 IEEE International Solid-State Circuits Conference3 of 24Contents IntroductionNAND ChallengesMerits of BV-NAND Architecture(IO,Bit-density)Key Features Key Design2-Transistor Coded-GSLStack-Dependent Pass-Voltage ControlExternal Power Assisted Core DrivingProp