专有互连和 CXL.pdf

1、1|2024 SNIA.All Rights Reserved.Proprietary Interconnects and CXLPresented by Larrie CarrVP Engineering,Rambus2|2024 SNIA.All Rights Reserved.CXL Specification Release TimelineCompute Express Link and CXL are trademarks of the Compute Express Link Consortium.2March 2019CXL 1.0 Specification Released

2、September 2019CXL Consortium Officially IncorporatesCXL 1.1 Specification ReleasedNovember 2020CXL 2.0 Specification ReleasedAugust 2022CXL 3.0 Specification ReleasedNovember 2023CXL 3.1 Specification Released3|2024 SNIA.All Rights Reserved.In the Beginning PCI Express Gen 1.0 was introduced in 2003

3、 Serial ATA in 2003 and Serial Attached SCSI in 2004 Coherent Accelerator Processor Interface(CAPI)in 2014 Focused on attaching specialized accelerators to the IBM Power processors Low-latency,coherency connectivity between processor and accelerator memories Leveraged PCIe Gen3 and later PCIe Gen4 O

4、penCAPI consortium created in 2016 to support all ISAs Cache Coherent Interconnect for Accelerators(CCIX)in 2018 Open cache-coherent interconnect extension to PCIe Simplify the communication between the processor memory and accelerators Leveraged PCIe Gen4,but supported faster non-standard link rate

5、s34|2024 SNIA.All Rights Reserved.Stranded Resources in 2014 NERSC analyzed the workloads on their HPC systems Hopper HPC(2010):32GB DRAM per node Edison HPC(2014):64 GB DRAM per node Cori HPC(2016):96GB DRAM,16GB HBM per node 8%of Edison workloads uses more than 80%of available memory per node 16%o

6、f Edison workloads would not run on Hoppers 32GB nodes 71%of Edisons workloads will fit within Coris HBM2014 NERSC Workload Analysis,Oct 20155|2024 SNIA.All Rights Reserved.Exascale Program DOE launched the Exascale Computing program in 2016 to accelerate the development of exascale HPC Prepare the