会议10_使用 CXL 实现系统可组合性.pdf

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1、System Composability Using CXLKurtis Bowman,Marketing Working Group Co-Chair,CXL ConsortiumMitch Wright,CXL System Architect,Liqid2024 OFA Virtual WorkshopRouterWirelessInterconnectMobileNetworksInter DC linksCore/EdgeNetworkSpine SwitchLeaf SwitchTOR SwitchWANDATA CENTERRACKPACKAGEDIERACKRACKRACKRA

2、CKRACKRACKData centerInterconnectSoCInterconnectNODEProcessorInterconnectCXL 1.1Single NodeCoherent interconnectData Center:Expanding Scope of CXLCXL 3.0/3.1Composable Fabric growth for disaggregation/pooling/accelerator Multiple Nodes inside a Rack/Chassis supporting pooling of resourcesCXL 2.0Comp

3、ute Express Link and CXL are registered trademarks of the Compute Express Link Consortium.CXL Specification Feature SummaryFeaturesCXL 1.0/1.1CXL 2.0CXL 3.0CXL 3.1Release date20192020August 2022November 2023Max link rate 32GTs32GTs64GTs64GTsFlit 68 byte(up to 32 GTs)Flit 256 byte(up to 64 GTs)Type 1

4、,Type 2 and Type 3 Devices Memory Pooling w/MLDs Global Persistent Flush CXL IDE Switching(Single-level)Switching(Multi-level)Direct memory access for peer-to-peer Enhanced coherency(256 byte flit)Memory sharing(256 byte flit)Multiple Type 1/Type 2 devices per root port Fabric capabilities(256 byte

5、flit)Fabric Manager API definition for PBR Switch Host-to-Host communication with Global Integrated Memory(GIM)concept Trusted-Execution-Environment(TEE)Security Protocol Memory expander enhancements(up to 34-bit of meta data,RAS capability enhancements)Compute Express Link and CXL are registered tr

6、ademarks of the Compute Express Link Consortium.Supported Not Supported4CXL 3.1 Fabric Management FeaturesCompute Express Link and CXL are registered trademarks of the Compute Express Link Consortium.Fabric Decode/Routing requirements Host-to-Host communication with Global Integrated Memory(GIM)conc