8-d3s2-1sc_app_class_riscv_china_aug_2023.pdf

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1、Copyright 2023 Syntacore.All trademarks,product,and brand names belong to their respective owners.Is RISC-V ready for the application class workloads?August 25,2023Alexander Redkin,CEOLisa Yang,APAC BD VPCopyright 2023 Syntacore.All trademarks,product,and brand names belong to their respective owner

2、s.About SyntacoreSemiconductor IP company,founding member of RISC-V foundationEst 2015,200+EEsState-of-the-art RISC-V CPU IP line with competitive features+turnkey customizationRISC-V client silicon in 2016,RISC-V Linux-capable IP in 2016,full-wafer from 2017Projects on 10+nodes at 5 foundries(230 t

3、o 5nm):IoT:active battery-less SoC 22nm(extensive power optimization,ntv-ready)HPC:50+cores heterogeneous SoC 7nm(64bit,NuMA,system arch customization)Copyright 2023 Syntacore.All trademarks,product,and brand names belong to their respective owners.SCRx product linePerformanceArea,powerSCR1SCR3SCR4S

4、CR5SCR7Linux/Full OSRTOS32-Bits64-Bits64b64b64bRV32I|EMCRV64IMCARV64IMCFDARV64IMCFDARV32IMCARV32IMCFDARV32IMCFDARV64IMCFDASCR6RV64IMCFDAM0-M3M4M55-M7M3-M33A5-A7A53-A55SCR9RV64IMCFDAA7xCopyright 2023 Syntacore.All trademarks,product,and brand names belong to their respective owners.State-of-the art R

5、ISC-V CPU IP familyBaseline cores:Clean-slate designs in System VerilogConfigurable and extensible100%compatible with major EDA flowsSilicon-proven at the customersCopyright 2023 Syntacore.All trademarks,product,and brand names belong to their respective owners.RV64 SCR9 Linux-capable application CP

6、U with entry-level server class features:8-16 cores per clusterSMP and heterogeneous(bigLittlew/SCR7)12 stage OoO pipelineCoherent NoC-based L3CHI external i/fSV39,SV48RVVRVBHypervisorAIARVA22Accelerators support 7+CM/MHz per core 2+GHz 7nm(*)some features may not be available in the initial release