通过金芯片验证和预硅相关性构建可互操作的芯片生态系统.pdf

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1、Michael Klempa,Alphawave SemiPedro Merlo,Keysight TechnologiesBuilding an Interoperable Chiplet Ecosystem through Golden Die Validation with Pre-silicon CorrelationBuilding an Interoperable Chiplet Ecosystem through Golden Die Validation with Pre-silicon CorrelationMichael Klempa,Alphawave SemiPedro

2、 Merlo,Keysight TechnologiesServer:Open Chiplet EconomyMotivation for Chiplet-based ArchitecturesData-center AI leads in chipletadoption due to the need for massive compute and bandwidth.Edge and Automotive AI are rapidly embracing chiplets to balance power,performance,and integration of diverse IP

3、blocksConsumer AI is smaller in volume integrating cutting-edge nodes with cost-effective I/O Connectivity Interface Comparison PCIe 7.0PCIe 7.0UALinkUALinkXSRXSRD2D Standard PD2D Standard Pkgkg:UCIe/BoWD2D D2D AdvancedAdvancedPkg:Pkg:UCIe/BoWUCIe 3DUCIe 3DHBMHBMObjective Objective Scale Up Scale Up

4、 Very Low LatencyVery Low LatencyScale Up Scale Up Very Low LatencyVery Low LatencyLocal ConnectionsLocal ConnectionsLow CostLow CostLocal ConnectionsLocal ConnectionsLow CostLow CostLocal ConnectionsLocal ConnectionsHigher Density/Higher Density/Higher costHigher costLogic to Logic Logic to Logic V

5、ery Wide I/FVery Wide I/FCompute to Memory Compute to Memory Wide I/FWide I/FPackage TechnologyPackage Technology2D Laminate2D Laminate2D Laminate2D Laminate2D Laminate2D Laminate2D Laminate2D Laminate2.5D Interposer2.5D Interposer3D Silicon Stacking3D Silicon Stacking2.5D Interposer2.5D InterposerP

6、HY ArchitecturePHY ArchitecturePAM4 SerDesPAM4 SerDesPAM4 SerDesPAM4 SerDesPAM4 SerDesPAM4 SerDesDDR Clock FWDDR Clock FWDDR Clock FWDDR Clock FWSDR/DDRSDR/DDRDDR Clock FWDDR Clock FWBondPadBondPad/Bump/Bump PitchPitch110mm110mm110mm110mm110mm110mm100100-130m130m25m25m-55m55m4.54.5-9m9m45m45m-55m55m