提升边缘到核心系统的时序弹性：从 White Rabbit 到 PCIe.pdf

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1、Greg ArmstrongAdvancing Timing Synchronization for PCI-SIG CEM 7.0 in AI,Edge,and Hyperscale Data CentersUllas KumarStability and Phase Noise Key elements to Data Center Synchronization Stability and Phase Noise Key elements to Data Center Synchronization Ullas KumarOCP-TAPTraditional Applications D

2、atabase syncTelecom data center requirementsAir interface requirements AI data center requirementsOverviewClocking&Synchronization is CriticalCompute&StorageSpine Switches Leaf SwitchesRemote RadioUnitsT-GMThe spine switches Upper LayerDistribution Transparent clock/boundary clocks The end clients N

3、ICsCPU/xPUSynchronization DistributionData Centre timing flowSpine SwitchesLeaf SwitchesServers400-800G and beyond InterfacesFree running interfaces Moving from generic XOs(20-50ppm)to high stability clocks Frequency stability(0.1ppm-1ppm)Absolute accuracy(5ppm/10 years)Absolute accuracyRecommended

4、accuracy is 20ppm 5ppm reduces the DSP loading for frequency correction Activity dips/frequency micro jumpsCreate link-down situationsSupport for Sync functions PTM or Boundary clocksImproved Clocking at Interconnects Introduced detection probability error Horizontal eye affected by jitter 12K-40MHz

5、Mid-band phase noise affects the vertical eyeIntroduces higher EVMCoherent systems Impact of Phase noise Ideal Constellation(Noise-Free)Noisy Constellation(High Phase Noise)HRM by OCPTransparent clocks Measure and adjust for resident time The stability of clocks not significant to resident time Late

6、st switches with 250ns 400ns latency The clock accuracies are many orders of magnitude better BCs need higher stability clocksRuns low bandwidth servosTarget low in-band traffic 1 packet per second or lower?SyncE may or may not be available Target Class D performanceTarget 0.1ppb/degC sensitivity re