对高性能计算 (HPC) 应用进行屋顶线分析和剖面分析以指导系统设计.pdf

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1、George Michelogiannakis(miheloglbl.gov)Patricia Gonzalez-Guerrero(lg4erlbl.gov)HPC and AI chiplet modularity workstream co-leadsRoofline Analysis and Profiling of HPC Applications to Guide Modular System DesignSERVER:OPEN CHIPLETECONOMYSpecialization Sustains Performance ScalingSpecialization Requir

2、es InvestmentsChiplet Modularity Makes Specialization AccessibleChiplets MarketplaceProfiling helps us pick a collection of chiplets(newly-developed or available from the community)for a set of applications,as well as their placementApplication Profiling Guides Chiplet DesignApplication characteriza

3、tionCollection of chiplets that maximize metric of interestOCPs chiplet modularity workstream members collected profiling results and performed literature searchWell present some insight from profiling efforts(the topic of this talk)You can join us to help shape this effort!Particle Tracking(ATLAS 2

4、6%in Perlmutter)Roofline Graph34GB memory occupancyAverage IPC 241%of instructions areloads or storesParallel and Serial RegionsLoad/Store HistogramDRAM Access LatencySimulated cache-aware annealing to optimize routing cost of a chip designSA approximates the global optimum in a large search spaceCa

5、nneal(PARSEC Benchmark Suite)Memory bandwidth(GB/s)21%of stalls due to memoryPower timeline.mJ/secProfiling AI AlgorithmsWe use these results to design a systolic array with chiplets.Join our workstream for more!Generate hardware description(models or RTL)or models for HPC and AI appsMap onto existi

6、ng or projected technological advancements in chiplets and packagingAlso,memory and I/O chiplets and protocolsDevelop a systematic mapping method for a set of chiplets in tiles and onto a 2D planeOngoing WorkPlease join us in shaping strate