XASM：使用 P4 对 X2 进行编程的基础.pdf

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1、XASM:A Foundation to Program the X2 with P4Fabian Ruffy,Vladimir GurevichCopyright2025 Xsight Labs.Public PresentationWhat is X2 and XISA?Why XASM?XASM ConceptsTo P4 and Beyond!Agenda2Copyright 2025 Xsight Labs.Public Presentation12.8Gbps Programmable Switch 400Gbps/200Gbps/100Gbps ports Additional

2、PCIe and Ethernet CPU portsEnsemble of Data Processing Units(DPUs)Programmable Parser Programmable Match-Action Processor(MAP)Packet buffer,SRAMs,TCAMsOpen Instruction Set Architecture(XISA)The X2 Switch3Source:https:/ 2025 Xsight Labs.Public PresentationTNA SwitchTofino Native Architecture(TNA)Ingr

3、ess pipelineEgress pipelinePacket ReplicationEngine&Traffic ManagerPacket IngressPacket Egresspacket_inpacket_inpacket_outpacket_outIngress HeadersIngress MetadataEgress HeadersEgress MetadataStraight-through packet flowPacket data Programmable InterfacesFixed(intrinsic)interfacesParserParserControl

4、DeparserControlDeparser4Copyright 2025 Xsight Labs.Public PresentationX2 Data PlaneFollows P4 Model:Fixed-function core with programmable portionsNo fixed compute budget,throughput and latency degrades commensurate with complexity.X2 Programming Model 5MAPASMMOV R0.0,R1.3BRBTSTSET R11.3,1,do_ipv4LKP

5、LPM.LF1 R5,R5,NS,NS,R4.4,PacketParserASMEXTMAP MAPR0,0,0,96EXTNTXP R3,96,16STHC 14,3,1,JUMP_NEXTPacketIngress PortEgress PortData Plane ProgramQueueManagerProgrammable packet flowEntry PointsPacket data Programmable InterfacesFixed(intrinsic)interfacesEntry PointsOverall Data Plane AlgorithmConfiden

6、tial|Copyright 2025 Xsight Labs.All Rights Reserved.An Open ISA and XASM6X-ISAP4XASMCopyright 2025 Xsight Labs.Public PresentationX2 Data PlaneParserASMEXTMAP MAPR0,0,0,96EXTNTXP R3,96,16STHC 14,3,1,JUMP_NEXTMAPASMBRBTSTSET R11.3,1,lkp_ethlkp_eth:LKP.LF1 R5,R5,NS,NS,0,Compiling A Data-Plane Program7