为人工智能的未来提供动力：面向人工智能加速器的高功率密度解决方案.pdf

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1、Surendhar SomasundaramPaul YeamanPowering the Future of AI:High Power Density Solutions for AI AcceleratorsCompute systems are thermally limitedAs GPU currents rise,heat from PDN losses limit compute powerLimiting PDN loss is critical to maximize compute powerLower core voltageBetter transient respo

2、nseEnable new compute architecturesWaferscaleenginesVertical Power Delivery(VPD)is necessary to minimize PDN lossesGrowing processor power requirements drive geometric PDN loss increaseVPD is required to keep pace with growing processor power demandPower Delivery Innovation:MotivationPower Delivery

3、Solutions for AI AcceleratorsModule(Vertical)Lumped PDN=10-15DiscretesubstrateMotherboardSOCModule(Lateral)substrateMotherboardSOCsubstrateMotherboardSOCsubstrateMotherboardSOCIntegrates power stage,inductor and capacitors into a single device,enabling more current to be sourced close to processorPD

4、N losses exceed 100W for GPU currents beyond 1100 1350ALowest cost,with established eco-system and quality recordPDN losses exceed 100W for GPU currents beyond 850-1000ALumped PDN=90-140Lumped PDN=55-80Module(Backside Lateral)Relocates the module to the backside of the motherboard,shortening the hig

5、h current path to GPUPDN losses exceed 100W for GPU currents beyond 1500 2000ALumped PDN=25-45Positions modules directly under processor,further shortening current pathPDN losses exceed 100W for GPU currents beyond 2500 3000AVR relocation under processor Improves PDN lossesAllows for more powerful G

6、PUsRequires significant system redesignBVMs will continue to improveMove closer to SOCImprove power densityChallenges will drive technology improvementsElectricalMechanical ThermalImpact of Vertical Power DeliveryGen 1 Module(Lateral):Dual Phase 160A,10 x9mm Higher Efficiency than equivalent discret