7.Test Generation for RISC-V HPC Verification Challenges.pdf

1、TestGenerationforRISC-VHPCVerificationChallengesYujieFan,ApplicationEngineer2025/7/18LegalDisclosureCONFIDENTIAL INFORMATIONTheinformationcontainedinthispresentationistheconfidentialandproprietaryinformationofSynopsys.Youarenotpermittedtodisseminateoruseanyoftheinformationprovidedtoyouwithouttheprio

2、rwrittenconsentofanauthorizedofficerofSynopsys.IMPORTANT NOTICEIntheeventinformationinthispresentationreflectsSynopsysfutureplans,includingbutnotlimitedtoSynopsysfinancialtargets,expectationsandobjectives;strategiesrelatedtoourproducts,technologyandservices;businessandmarketoutlook,businessopportuni

3、tiesandstrategies;andmore,suchinformationisbasedoncurrentestimates,providedasofthedateofthispresentationandaresubjecttochange.Synopsysundertakesnodutyto,anddoesnotintendto,updateanyforward-lookingstatement,whetherasaresultofnewinformation,futureeventsorotherwise,unlessrequiredbylaw.2025Synopsys,Inc.

4、3AgendaVerificationChallengesforHPCImplementationsRISC-VFeaturesforHPCUse-CasesSTINGMechanismsforRISC-VHPCDesignVerificationBugsFoundSynopsysConfidentialInformation2025Synopsys,Inc.4SynopsysConfidentialInformationVerificationChallengesforHPCImplementations2025Synopsys,Inc.5Multi-die/SoftwareFromCPUS

5、ubsystemsChipletsMulti-dieSystemsFull Chip(let)/SoftwareSubsystem/SoftwareIP/Core Centric*“SystemValidationatARM:EnablingourPartnerstoBuildBetterSystems”,https:/bit.ly/3WLCvhr,https:/bit.ly/3CEMBd0HBMHBMHBMHBMHBMHBMHBMHBMIOChipletSRAMSRAMSRAMSRAMSRAMSRAMSRAMSRAMSRAMSRAMSRAMSRAMSRAMSRAMSRAMSRAMAIBoos

6、terAIBoosterClusterBoosterClusterBoosterHBMHBMHBMHBMHBMHBMHBMHBMIOChipletOpticalIOPeripheralPeripheralMemoryBasicPeripherals(Uart,I2C)MemoryCPUClusterBusFabrics/NoCsMemoryAIAccelerator(NPU)MemorySensorsEmbeddedProcessorsMemoryInterfaceSecurityIPSystemInterfaces(PCIe,Ethernet,)PeripheralInterfaces(US