内存池类型：RISC-V 多核集群中的多功能性和专业化之间.pdf

1、pulp-platform.orgpulp_ PlatformOpen Source Hardware,the way it should be!company/pulp-platformIntegrated Systems Laboratory(ETH Zrich)MemPoolFlavors:Between Versatility andSpecialization in a RISC-V Manycore ClusterSergio Mazzolasmazzolaiis.ee.ethz.chYichao ZhangMarco BertulettiDiyou ShenLuca Benini

2、The shared-memory clusterWidely used building blockParallelism,flexibilityLow-latency access SPMMulti-bankedEfficient communication+synchronizationFast logarithmic interconnectEfficient coresIndividually programmableISA extensionsHide SPM residual latencyRISC-V Summit 2025,May 15th,20252CoreCoreCore

3、CoreLogarithmic InterconnectScratchpad MemoryBankBank Bank Bank Bank Bank Scale-upvs.scale-outLarge workloads many cores+big memoryMore clusters?Bigger single cluster!Low-latency memory accessReduce overhead of data chunks transferKeep high compute utilizationPhysically-feasible interconnectEasy to

4、programRISC-V Summit 2025,May 15th,20253Local Network-on-ChipL1BankCoreloc-NoCCoreL1BankScale-UpScale-Outa).b).Global NoCLocal Network-on-ChipL1BankCoreloc-NoCCoreL1BankScale-UpScale-Outa).b).Global NoCThats difficult!How do we scale up?RISC-V Summit 2025,May 15th,20254https:/ TPUCustom acceleratorS

5、pecializedscalableNVIDIA Ampere GPUSIMTComplex mem hierarchyFlexibleAMD EPYC CPUShared-memMax flexibilityDoesnt scaleMemPoolversatileMemPool:Open-source,RISC-V-based manycore clusterSmall,flexible cores256+RISC-V cores1+MiB of shared L1 data memory 5 cycles latencywithout contentionThanks to hierarc

6、hical architecturePhysical-aware designWC Frequency 500 MHzOpen-sourceRISC-V Summit 2025,May 15th,20255MemPool FlavorsRISC-V Summit 2025,May 15th,20256MemPoolVectorialMemPoolITAMemPoolSystolicMemPoolTeraPoolNoCTeraPoolCacheP FlavorsRISC-V Summit 2025,May 15th,20257MemPoolVectorialMemPoolITAMemPoolSy