1、Unleashing the Power of RISC-V E-Tracewith a Highly Efficient Software Decoder13 May 2025Unrestricted|Siemens 2025|Siemens Digital Industries Software|Marcel Zak,Mat ODonnell,Vivek Chickermane|RISC-V Summit Europe 2025AgendaWhat is Trace?Case StudiesDecoding SpeedPython APICustom Instruction Decodin
2、gSummaryUnrestricted|Siemens 2025|Siemens Digital Industries Software|Marcel Zak,Mat ODonnell,Vivek Chickermane|RISC-V Summit Europe 2025Page 2What is Trace?Unrestricted|Siemens 2025|Siemens Digital Industries Software|Marcel Zak,Mat ODonnell,Vivek Chickermane|RISC-V Summit Europe 2025Page 3Provides
3、 visibility for the processor behaviourTraditional techniques stops the processorSampling adds operations and not full visibilityIn many applications traditional techniques dont work anymoreTime critical applicationsHeisenbug bugsComplex SoC with multiple coresComplement other debugging toolsIt is a
4、 technique for monitoring the activity of your processor inan unintrusive way.real-timeeventsperipheralssub-optimalimplementationsbugsCPU-CPUinteractionsSoftwarebehaviorWhat is Trace?Unrestricted|Siemens 2025|Siemens Digital Industries Software|Marcel Zak,Mat ODonnell,Vivek Chickermane|RISC-V Summit
5、 Europe 2025Page 4GPUDRAMcontrollerCustomLogicDSPJTAGUSB 2/3System Memory BufferMessage EngineSOC InterconnectEnhancedTraceEncoderTraceDebugOff-Chip Decode/Trace CaptureAXI/PCIEDecompressionCompression 700 xCase Study:Seagate Hard Drive SoC Motion Control ApplicationUnrestricted|Siemens 2025|Siemens
6、 Digital Industries Software|Marcel Zak,Mat ODonnell,Vivek Chickermane|RISC-V Summit Europe 2025Page 5Microarchitecture optimization,parallelism,and latency reductionSeagate RISC-V CoreLegacy CoreDisturbance detection filter(computational cycles)3 ReductionRISC-V-Enabled SolutionFunctional Example:H