20250121_PreConE_Joly.PDF

1、Simplifying the Use of Co-Packaged Optics with ChipletsSylvie JOLYPartnerships Manager 3D integration&PackagingThe computing power required for AIis doubling every 100 days andis projected to increase by more thana million times over the next 5 yearsZhu&al,Intelligent computing,2023Photo:28/10/2022E

2、xemple de pied de page(A modifier dans longlet Insertion/En-tte/Pied3AI Performance challengesMemory and Interconnect WallAI and Memory WallAmir Gholami,UC Berkeley,Berkeley,CA,94720,USAPhoto:28/10/2022Exemple de pied de page(A modifier dans longlet Insertion/En-tte/Pied4Packaging&Chiplet answer to

3、performance?Intel Clearwater Forest for Server CPUAMD MI300 for AIAWS Graviton4Nvidias BlackwellBroadcomChiplets and Interposers becoming mainstreamScale-out at package levelHeterogeneous integrationRecover yieldpartitioning creates communication bottlenecksOptical reach went from 100km to 100m to m

4、 to board-levelWhat opportunities down to chip-level?Die-to-die optical links:the right technology for interposer-level communication!Relieve constraints of dense on-chip interconnectsReduce latency created by distance&routingImprove performance&power by overcoming latency overheadsAppl.Phys.Lett.20

5、21(Broadcom,UCSB,Intel)Enabling Communication technology roadmapEnabling Communication technology roadmapMature CMOS ecosystem applied to silicon photonicModern packaging and 3D integration Up to optical links for chiplets on interposer Bring silicon-photonic and microelectronic world together Integ

6、rationModern foundries are in 300mm and InP/GaAs in lower wafer sizeDesign ecosystem capabilities,development of assembly PDKs,and thermal design managementHigh Yield required for co-integration of 100s of devices together.Reliability:laser implementation is still an issues,most PIC use desagragated