15-d3s3-2-SiFive_Discovering the RVV C intrinsics API v1.0_eop Chen.pdf

1、2023 SiFiveDiscovering the RVV C intrinsicsAPI v1.0eopChenKitoCheng2023 SiFive2CreditsThe development of RVV intrinsics owes a great debt to Nick Knight,Craig Topper,and Roger Ferrer Ibez for their valuable comments and reviews.2023 SiFive3AbstractIntroductionAvailability and usageTest macro and hea

2、der inclusionCurrent status of support in the upstream compiler toolchainControl to the vector extension programming modelOverviewExplicit(non-overloaded)intrinsicsImplicit(overloaded)intrinsicsOther variantsCurrent status and planning2023 SiFive4Availability and usageCurrent status of support in th

3、e upstream compiler toolchainLLVMLLVM 16 0 supports the v0.11 intrinsicsLack the tuple-type segment load/store,the floating-point rounding mode intrinsics,and the fixed-point rounding mode intrinsics.LLVM 17 1 supports the v0.12 intrinsicsExpecting no more change to the specification and identical t

4、o what is in v1.0GCCThe next GCC release(GCC 14)2 is expected to support v1.00 https:/releases.llvm.org/16.0.0/tools/clang/docs/ReleaseNotes.html1 https:/ https:/gcc.gnu.org/releases.html2023 SiFive5Availability and usageTest macro and header file inclusionUsers can check the compiler support throug

5、h the testing macro _riscv_v_intrinsic.Please include to access the RISC-V vector intrinsics.#ifdef _riscv_v_intrinsic#include#endif/*_riscv_v_intrinsic*/2023 SiFive6Control to the vector extension programming model Overview-Starting from the vsetvl configuration(1)Decision on the level of abstracti

6、on Starting from the essential instruction in the vector extension2023 SiFive7Control to the vector extension programming model Overview-Starting from the vsetvl configuration(2)Decision on the level of abstraction Starting from the essential instruction in the vector extensionIntrinsics brings asse