1A-101_Implementing a Fourth Generation SmartNIC Netronome.PDF

1、Fourth Generation Architecture for SmartNICsJim Finnegan&Niel Viljoen&San Jose,CA April 26-28,2022“Conflicting Requirements”“Conflicting Requirements”conundrumGeneralized intent of SmartNICs is to“offload certain functions from host”how can this be accomplished cost-effectively?(review the evolution

2、 of implementation options)how can the offloaded functions be flexibly adjusted?(implies software programmability)how can the solution address exponentially increasing bandwidth link speeds?(implies the need for scalability)how can the implementation leverage and incorporate domain specific elements

3、?(implies adoption of open standards and 3rdparty integration)how can the solution meet the power-performance-area dichotomy?(implies cognizance of Dennard Scaling and Moores Law through use of chiplets)2San Jose,CA April 26-28,2022First Generation First Generation SmartSmartNICsNICs3 First generati

4、on SmartNICs(sic)offloaded rudimentary stateless functions such as CRC,RSS,etc.TOE was first example of stateful offload Most of the network processing was still done in the host 1stgeneration referred to as“BasicNIC”or“CoreNIC”Rudimentary offloads didNOT comprehend state These NICs did not have int

5、elligence to send pkts to egress port without traversing PCIe(perf.impact)Historical footnote TCP/IPtemporarily overshadowedin 1990s by jitter tolerant ATM(Asynchronous TransferMode)San Jose,CA April 26-28,2022Second Generation SmartNICsSecond Generation SmartNICs4 Aka“Offload-”/“Feature-”NIC Accele

6、ration can be in-line or side-looking Accelerator can add Meta-data to packets if in-line NIC function needs multiple interfaces to classify and steer traffic FPGA or NPU may additionally offload selected NIC functions 2ndGeneration generally referred to as“Offload NIC”State processing added viaNPUs