HC2022.PNNL.Curzel.v01.pdf

1、From High-Level Frameworks to custom Silicon with SODASerena Curzel,Nicolas Bohm Agostini,Reece Neff,Ankur Limaye,Jeff(Jun)Zhang,Vinay Amatya,Marco Minutoli,Vito Giovanni Castellana,Joseph Manzano,David Brooks,Gu-Yeon Wei,Fabrizio Ferrandi,Antonino Tumeo2Overview The SODA Synthesizer is a modular,mu

2、lti-level,interoperable,extensible,open-source hardware compiler from high-level programming frameworks to silicon Compiler-based frontend,leveraging the MultiLevelIntermediate Representation(MLIR)Compiler-based backend,leveraging state-of-the-art High-Level Synthesis(HLS)techniques Generates synthe

3、sizable Verilog for a variety of targets,from Field Programmable Gate Arrays(FPGAs)to Application Specific Integrated Circuits(ASICs)Optimizations at all levels are performed as compiler optimization passes3ResultsUseful linksASIC accelerators for LeNet layersSODA-OPTSODA Docker ImagePanda-Bambu HLS

4、(v 0.9.7)SODA Tutorial:DATE 20224Motivations Data Science algorithms,Machine Learning models and frameworks are quickly evolving Increased complexity and tight performance/power/area constraints(especially on edge devices)require domain-specific acceleratorsY.Lecun,et al.,“Gradient-based learning ap

5、plied to document recognition,”Proc.IEEE,1998Increasing number of layers and parametersNew network architecturesCompression techniquesNew programming environments(ResNet VGG,Transformers)(GNN,LSTM,Reinforcement Learning)(Quantization,pruning)(TensorFlow,PyTorch,MXNet)5Motivations Existing accelerato

6、rs start from specific models(e.g.,CNNs)or only try to accelerate specific computational patterns Designing hardware accelerators by hand is complex and time-consuming Hardware designers may want to explore different design trade-offs,depending on the application requirements Agile Hardware Design a