Session8_Die-to-Die and High-Speed Electrical Transceivers.pdf

1、ISSCC 2026SESSION 8Die-to-Die and High-Speed Electrical Transceivers 2026 IEEE International Solid-State Circuits Conference1 of 298.1:A 48Gb/s/lane 1.24Tb/s/mm UCIe-Compliant Die-to-Die Link Over 30mm Standard PackageA 48Gb/s/lane 1.24Tb/s/mm UCIe-Compliant Die-to-Die Link Over 30mm Standard Packag

2、eSusnata Mondal*,Sashank Krishnamurthy*,Shuhei Yamada,Zhaokai Liu,Junyi Qiu,Soumya Bose,Zuoguo Wu,Gerald Pasdast,James Jaussi,Mozhgan MansuriIntel Corporation,Hillsboro,OR&Santa Clara,CACurrently with UC Santa Cruz*Equally contributing authors 2026 IEEE International Solid-State Circuits Conference2

3、 of 298.1:A 48Gb/s/lane 1.24Tb/s/mm UCIe-Compliant Die-to-Die Link Over 30mm Standard PackageOutline Introduction&Motivation:Die-to-Die UCIe-S Transceiver Circuit Architecture and InnovationsClock:Compact resonant clock,low-power de-skewTX:Impedance-invariant CTLE,high-swing driver RX:Enhanced latch

4、,supply noise rejection Measurement Results48Gb/s UCIe-S compliant rate 56Gb/s extended rate ConclusionUCIe Universal Chiplet Interconnect ExpressUCIe-S UCIe over Standard packageCTLE Continuous Time Linear Equalizer 2026 IEEE International Solid-State Circuits Conference3 of 298.1:A 48Gb/s/lane 1.2

5、4Tb/s/mm UCIe-Compliant Die-to-Die Link Over 30mm Standard PackageWhy UCIe Die-to-Die Link?Why die disaggregation?limits of monolithic SoC scaling avoid large die&better yield technology heterogeneityWhat package&circuit challenges?ultra low power low latency supply noise rejection crosstalk mitigat

6、ion ultra compact(high shoreline bandwidth density)UCIe standard enables interoperabilityUCIe-S:over standard organic pkgUCIe-S on-pkg interconnectUCIe-S die-to-die link 2026 IEEE International Solid-State Circuits Conference4 of 298.1:A 48Gb/s/lane 1.24Tb/s/mm UCIe-Compliant Die-to-Die Link Over 30