Session11_Pipeline and Ultra-High-Speed Data Converters.pdf

1、ISSCC 2026SESSION 11Pipeline and Ultra-High-Speed Data Converters11.1:A 14b 400MS/s TDC-Assisted Pipelined-SAR ADC with Rail-to-Rail Input VTC and Background Time-Domain Error Calibration 2026 IEEE International Solid-State Circuits Conference1 of 54A 14b 400MS/s TDC-Assisted Pipelined-SAR ADC with

2、Rail-to-Rail Input VTC and Background Time-Domain Error CalibrationJingpeng Wang1,Bingrui Li1,Haoyang Luo1,Mingtao Zhan2,Xiyu He2,Dawei Shen1,Lu Jie2,Xiyuan Tang11Peking University,Beijing,China,2Tsinghua University,Beijing,China11.1:A 14b 400MS/s TDC-Assisted Pipelined-SAR ADC with Rail-to-Rail Inp

3、ut VTC and Background Time-Domain Error Calibration 2026 IEEE International Solid-State Circuits Conference2 of 54Outline Motivation Proposed TDC-Assisted ADC2-step Time-domain Frontend QuantizerTime-domain Error Calibration Method Circuit Implementation Measurement Results Conclusion11.1:A 14b 400M

4、S/s TDC-Assisted Pipelined-SAR ADC with Rail-to-Rail Input VTC and Background Time-Domain Error Calibration 2026 IEEE International Solid-State Circuits Conference3 of 54Motivation SAR based sub-ADC in Pipeline ADCN decision for N-bitBit cycling time limits stage speed 11.1:A 14b 400MS/s TDC-Assiste

5、d Pipelined-SAR ADC with Rail-to-Rail Input VTC and Background Time-Domain Error Calibration 2026 IEEE International Solid-State Circuits Conference4 of 54Motivation Flash TDC based sub-ADC in Pipeline ADC1 parallel decision for N-bitSpeed enhancement compared with SAR sub-ADC 11.1:A 14b 400MS/s TDC

6、-Assisted Pipelined-SAR ADC with Rail-to-Rail Input VTC and Background Time-Domain Error Calibration 2026 IEEE International Solid-State Circuits Conference5 of 54Motivation Flash TDC based ADC DisadvantagesPVT variation of V-T conversion gain and offset Calibration is needed11.1:A 14b 400MS/s TDC-A