Session15 DRAM, SRAM, and Non-Volatile Memories.pdf

1、ISSCC 2026SESSION 15DRAM,SRAM,and Non-Volatile Memories15.1:A 2Tb 4b/Cell 6-Plane 3D-Flash Memory with 37.6Gb/mm2 Bit Density and 85MB/s Write Throughput 2026 IEEE International Solid-State Circuits Conference1 of 31A 2Tb 4b/Cell 6-Plane 3D-Flash Memory with 37.6Gb/mm2Bit Density and 85MB/s Write Th

2、roughputJayanth M Thimmaiah1,Ryuji Yamashita2,In-Soo Yoon3,Jason Li3,Cynthia Hsu3,Takuya Ariki2,Naoki Ookuma2,Yosuke Kato2,Koichiro Hayashi2,Kazuki Yamauchi2,Indra K V1,Masahiro Kano2,Sirisha Bhamidipati1,SnehaBhatia1,Seema Malhotra1,Naoki Ojima2,Ella Wu3,Zhiyong Yang3,Frank W Tsai3,Mathias Bayle2,N

3、aoyukiMinami2,Yasuyuki Fujihara2,Kei Kitamura2,Tomofumi Kitani2,Takuyo Kodama4,Takaya Handa4,NaoakiKanagawa4,Yuki Ishizaki4,Susumu Fujimura4,Yoshinao Suzuki4,Mario Sako4,Yumi Higashi4,YoshihisaWatanabe4,Toshiyuki Kouchi4,Aravinth V1,Chin-Yi Chen3,Xiang Yang3,Guirong Liang3,Jenny Wang31Sandisk,Bengal

4、uru,India,2Sandisk,Yokohama,Japan,3Sandisk,Milpitas,CA,4KIOXIA,Yokohama,Japan15.1:A 2Tb 4b/Cell 6-Plane 3D-Flash Memory with 37.6Gb/mm2 Bit Density and 85MB/s Write Throughput 2026 IEEE International Solid-State Circuits Conference2 of 31Outline Introduction Chip Architecture&Key Feature Comparison

5、Key Design ItemLocal BUS(LBUS)Coupling Sense Adequately Reduced Verify Fast Self Adjusting Read(FSAR)Fast SLC Burst ProgrammingBus Idle Sleep Mode Conclusion15.1:A 2Tb 4b/Cell 6-Plane 3D-Flash Memory with 37.6Gb/mm2 Bit Density and 85MB/s Write Throughput 2026 IEEE International Solid-State Circuits

6、 Conference3 of 31Outline Introduction Chip Architecture&Key Feature Comparison Key Design ItemLocal BUS(LBUS)Coupling Sense Adequately Reduced Verify Fast Self Adjusting Read(FSAR)Fast SLC Burst ProgrammingBus Idle Sleep Mode Conclusion15.1:A 2Tb 4b/Cell 6-Plane 3D-Flash Memory with 37.6Gb/mm2 Bit